7
2.2 SDRAM
U6200 [sheet 6, B/C7] is a 128Mbit with 32-bit bus wide synchronous dynamic random access
memory (SDRAM) IC. For SDRAM accesses, a memory clock of up to 166 MHz that synchro-
nizes data access is sent to the chip at pin 68. Data commands for accesses are coded in the
M_RAS_L and M_CAS_L signals (pins 18 and 19), and data read/write selection is done by the
M_WE_L signal (pin 17). The address to be written or read is given on the address bus
MA[10:0]. The 32-bit data bus MD[31:0] contains the word to be written or read after the pipeline
delay of the memory chip.
2.3 FLASH
U6203 [sheet 6, C3] is a 32Mbit with 16-bit bus wide Flash memory IC but only 8-bit wide data
bus is used in the system due to the limitation of CS98200. U6203 shares the memory address
with SDRAM (U6200) but the data is a dedicated one from CS98200. Flash access is asynchro-
nous and does not use a memory clock.
U6204 and U6205 [sheet 6, 4A-D] are buffers between the SDRAM and FLASH, and they have
their Output Enable pins tied to common pull-down resistors, with test points, allowing the
manufacturing plant to disable these buffers (thus releasing the FLASH address/data bus)
during programming. Half of buffer U6204 (2A/B[1..8]) is used to condition the 8 memory
control signals, and is given its own enable and direction-control signals (with independent test
points). This allows the manufacturing plant to maintain control of the SDRAM during both write
and read-back phases of In-circuit test.
2.4 ROMULATOR
J6200 [sheet 6, B/C2] is the ROMULATOR connector for the debug purposes of software
development. The console Main board provides a footprint for the required 60-pin ROMULATOR
connector but not populated in production. This connector will allow access to the FLASH
address and data busses, as per the Cirrus reference design. Pin 59 shall be tied into the
console reset circuitry, allowing it to access the CS98200 and keep the console FLASH in reset
while running off the ROMULATOR.
U6203 can be programmed not only from the ROMULATOR connector during development but
also from CD/DVD driver in the field. During re-programming in the field via CD/DVD driver, the
operating and new program are held in SDRAM. Power failures during field Flash update could
result in the console being made completely inoperable.
THEORY OF OPERATION
