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THEORY OF OPERATION
Output Board (Schematic 202H-3D)
DC CONTROL CURCUITS
The PEAK LEVEL signal is received via P2 from the Peak Level DAC on the Interface board. This dc
voltage ranges from 0 V to -3 V, corresponding to an output pulse magnitude of 0 V to 300 V.
The voltage produced by the high voltage power supply, PS1, is controlled by PEAK LEVEL, via the high
gain filter Z3B and translator Q2. The output of PS1 is monitored by a 100:1 divider, R40, R43, and R59.
A precision inverter, Z10B, Z11 Q23 and Z4, gives the proper polarity to this feedback signal before it is
combined with the DAC signal at Z3B. When the loop is balanced, the feedback level is equal to the
PEAK LEVEL signal from the DAC.
When a change in programmed level occurs, Z6, a bipolar differentiator, disables the high gain loop with
clamp Z4D which prevents Z3B from operating. A rough approximation of the control voltage is provided
by Z3A and fed via translator Q2 to the control input of the high voltage supply, PS1 pin 3. This brings
the output level near the intended range. When the output has settled, Z6 enables the feedback loop for
accurate adjustment of the output level.
The polarity of the output pulse is selected manually by switch SI. This grounds one of the output
terminals of the high voltage supply, PS1, selects the appropriate configuration of the output FET, Q7,
and connects the power supply feedback to the ungrounded power supply terminal.
Opto isolator Z12, when activated by comparator Z7, turns on FET Q26. This discharges the high voltage
storage capacitor, C701, by putting a high power load, R23, across the power supply terminals. This
allows the supply to drop quickly in level when needed, such as when the programmed level is dropped
or when circuit protection is required (as in the event of a power failure).
Z10A, Q22 and associated circuitry drive the front panel polarity LEDs, DS801 and DS802. The
appropriate LED turns on to indicate polarity, and blinks to indicate an overload condition.
Drive Circuits
Receiver Z8C accepts the ECL level DRIVE signal from the 6040 mainframe. The signal is differentiated
to provide short pulses coincident with the leading (Z8B) and trailing (Z8A) edges of the DRIVE signal.
These pulses are translated to TTL levels by Z9A and Z9B.
