________________________________________________________________________________________________________________________________________________
•
Dynamic voltage and frequency scaling
by scaling the voltage and frequency to optimize performance.
•
Multimedia powerhouse—
multilevel cache system, NEON™ MPE (Media Processor Engine) co
programmable smart DMA (SDMA) controller.
•
Powerful graphics acceleration
processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1
accelerator.
•
Interface flexibility—The processor supports connections to a variety of interfaces: LCD
controller, CMOS sensor interface (parallel), high
host PHY, multiple expansion card ports (high
Ethernet controller, and a variety of other popular interfaces (such as UART, I2C, and I2S serial
audio).
•
Electronic Paper Display Controller
color and monochrome with up to 2048 x 1536 resolution at
resolution at 20 Hz refresh and 5
•
Advanced security—The processor delivers hardware
secure e-commerce, digital rights management (DRM), informa
secure software downloads. The security features are discussed in detail in the i.MX 6SoloLite
security reference manual (IMX6SLSRM).
•
Integrated power management
internally all the voltage levels for different domains. This significantly simplifies system power
management structure.
•
GPIO with interrupt capabilities
and 3.06V supplies. The GPIO i
The i.MX 6 SoloLite processor is based on ARM Cortex
following features:
•
ARM Cortex-A9 MPCore CPU processor (with TrustZone)
•
The core configuration is symmetric, where each core includes:
—
32 KByte L1 Instruction Cache
—
32 KByte L1 Data Cache
—
Private Timer and Watchdog
—
Cortex-A9 NEON MPE (Media Processing Engine) co
The ARM Cortex-A9 MPCore complex includes:
•
General Interrupt Controller (GIC) with 128 interrupt support
•
Global Timer
•
Snoop Control Unit (SCU)
•
256 KB unified I/D L2 cache
•
Two Master AXI (64-bit) bus interfaces output of L2 cache
•
Frequency of the core (including NEON and L1 cache)
•
NEON MPE coprocessor
—
SIMD Media Processing Architecture
—
NEON register file with 32x64
—
NEON Integer execute pipeline (ALU, Shift, MAC)
—
NEON dual, single
—
NEON load/store and permute pipeli
following additional components:
HB5 Touch Computer
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Dynamic voltage and frequency scaling—The processor improves the power efficiency of devices
and frequency to optimize performance.
—The multimedia performance of each processor is enhanced by a
multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, and a
programmable smart DMA (SDMA) controller.
ul graphics acceleration—The processor provides three independent, integrated graphics
processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1
processor supports connections to a variety of interfaces: LCD
controller, CMOS sensor interface (parallel), high-speed USB on-the-go with PHY, high
host PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100 Mbps
et controller, and a variety of other popular interfaces (such as UART, I2C, and I2S serial
Electronic Paper Display Controller—The processor integrates EPD controller that supports E
color and monochrome with up to 2048 x 1536 resolution at 106 Hz refresh, 4096 x 4096
resolution at 20 Hz refresh and 5-bit grayscale (32-levels per color channel).
The processor delivers hardware-enabled security features that enable
commerce, digital rights management (DRM), information encryption, secure boot, and
secure software downloads. The security features are discussed in detail in the i.MX 6SoloLite
y reference manual (IMX6SLSRM).
Integrated power management—The processor integrates linear regulators and generate
ernally all the voltage levels for different domains. This significantly simplifies system power
GPIO with interrupt capabilities—The GPIO design supports configurable dual voltage rails at 1.8V
GPIO is configurable to interface at either voltage level.
SoloLite processor is based on ARM Cortex-A9 MP Core multicore processor, which has the
A9 MPCore CPU processor (with TrustZone)
The core configuration is symmetric, where each core includes:
32 KByte L1 Instruction Cache
32 KByte L1 Data Cache
Private Timer and Watchdog
A9 NEON MPE (Media Processing Engine) co-processor
A9 MPCore complex includes:
al Interrupt Controller (GIC) with 128 interrupt support
Snoop Control Unit (SCU)
256 KB unified I/D L2 cache
bit) bus interfaces output of L2 cache
Frequency of the core (including NEON and L1 cache)
SIMD Media Processing Architecture
NEON register file with 32x64-bit general-purpose registers
NEON Integer execute pipeline (ALU, Shift, MAC)
NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
NEON load/store and permute pipeline The SoC-level memory system consists of the
following additional components:
Touch Computer
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The processor improves the power efficiency of devices
The multimedia performance of each processor is enhanced by a
processor, and a
processor provides three independent, integrated graphics
processing units: 2D BLit engine, a 2D graphics accelerator, and dedicated OpenVG™ 1.1
processor supports connections to a variety of interfaces: LCD
go with PHY, high-speed USB
speed MMC/SDIO host and other), 10/100 Mbps
et controller, and a variety of other popular interfaces (such as UART, I2C, and I2S serial
The processor integrates EPD controller that supports E-INK
106 Hz refresh, 4096 x 4096
enabled security features that enable
tion encryption, secure boot, and
secure software downloads. The security features are discussed in detail in the i.MX 6SoloLite
The processor integrates linear regulators and generate
ernally all the voltage levels for different domains. This significantly simplifies system power
The GPIO design supports configurable dual voltage rails at 1.8V
Core multicore processor, which has the
precision floating point execute pipeline (FADD, FMUL)
level memory system consists of the
