Blu DASH 3.5, Руководство по обслуживанию

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3) Higher performance five-stage pipeline, Harvard cached architecture
4) Higher internal CPU clock rate with on-chip cache
5) Internal watchdog and sleep timers
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QDSP5000 350 MHz application digital signal processing (ADSP)
1) 512 KB L2 cache
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QDSP4000 122.88 MHz modem digital signal processing (MDSP)
Memory support features
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256 KB internal memory (IMEM) for graphics, internal functions, DSP, etc.
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Dual-memory buses separating the high-speed memory subsystem (EBI1) from
low-speed peripherals (EBI2) such as LCD panels
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Enhanced EBI1 memory support: 200 MHz bus clock for DDR SDRAM
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EBI2 support:
1) 1.8V memory interface support
2) Support for EBI2 A-D mixed mode
3) NAND flash memory interface
4) Support for 8-bit BCH ECC
5) Boot from NAND (One NAND not supported)
6) LCD
2.4 Power Management circuit
The PM8029 device integrates all wireless handset power-management, general house -keeping,
and user-interface support functions into a single mixed-signal IC.
This mixed-signal BiCMOS device is available in the 140-pin Wafer Level Nano-Scale
Package (140 WLNSP), which includes several ground pins for electrical ground and thermal
relief.
Power management functional block diagram as following: