NF325-A9 BIOS SETUP
15
DRAM Configuration
Figure 4.1 DRAM Configuration
Timing Mode
DDR Timing Setting by SPD or ITEM.
The Choices: Auto
(default), Manual.
Memclock index value (MHz)
Places an artifical memory clock limit on the system. Memory is prevented
from running faster than this frequency.
The Choices: 100
(default), 166, 133, 200.
CAS# Latency (Tcl)
This field specify the cas# latency, i.e. cas# to read data valid.
The Choices:
CL=2.0 (default), CL=3.0, CL=2.5,
RAS# to CAS# Delay (Trcd)
This field specifies the RAS# to CAS# Delay to read/ write command to the same
bank. Typically -20 Nsec.
The Choices: Auto
(default), 2 BUS CLOCKS, 3 BUS CLOCKS, 4 BUS
CLOCKS, 5 BUS CLOCKS, 6 BUS CLOCKS, 7 BUS CLOCKS.
Min RAS# active time (Tras)
This field specifies the minimum RAS# active time. Typically -45-60 Nsec.
The Choices: Auto
(default), 6 BUS CLOCKS,13 BUS CLOCKS, 14 BUS
CLOCKS, 15 BUS CLOCKS.
