BIPV8M-IAE
43
3.5 C
HIPSET
M
ENU
This submenu allows you to configure the specific features of the chipset installed
on your system. This chipset manage bus speeds and access to system memory
resources, such as DRAM. It also coordinates communications with the PCI bus.
Notice
z
Beware of that setting inappropriate values in items of this menu may cause
system to malfunction.
BIOS SETUP UTILITY
Main
Advanced
PCIPnP
Boot
Chipset
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
Advanced Chipset Settings
WARNING: Setting wrong values in below sections
may cause system to malfunction.
> South Bridge Configuration
> North Bridge Configuration
Exit
Configure North Bridge
features.
North Bridge Configuration
BIOS SETUP UTILITY
Chipset
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
North Bridge Chipset Configuration
PEG Port Congiguration
Configure DRAM Timing by SPD [Enabled]
DRAM CAS# Latency [5]
DRAM RAS# to CAS# Delay [6 DRAM Clocks]
DRAM RAS# Precarge [6 DRAM Clocks]
DRAM RAS# Activate to Precha [15 DRAM Clocks]
Initate Graphic Adapter [PCI/IGD]
Internal Graphics Mode Select [Enabled,8MB]
> Video Function Configuration
PCI MMIO Allocation:
DRAM Frequency [Auto]
Options
Auto
667 MHz
