INSTALLATION AND OPERATION GUIDE
Configuring the XIP-3901-UC / -DC / -FS Applications
64 | XIP-3901
You may switch between signals A, B or C, without any glitches, and also between the D<->E and F<->G signals.
Any other transition, like A<->D, will cause a vertical image shift for one frame.
To determine whether a clean hot switch is possible, you need to determine whether the two sources lie in the
same clean switch region. You can measure the position of the signals with respect to the reference:
Use the deglitcher tab in iControl (Video Input/Output -> Deglitcher)
When the deglitcher is enabled, the alignment offset between the reference signal and the input signal can be
displayed for either of these sources. Knowing the offset for both input signals, you can determine if they are in
the same clean switch region. If so, any hot switch between those two signals will be glitch-free.
To determine the limits of a clean switch region, you must know the input’s line length in μs. The first region is
delimited by +½ line and -½ line of the reference. For example, with an HD (1080i59) signal, the line length is
29.65 μs and so the first region lies between -14.83 μs and 14.83 μs. Other regions can be found by adding or
removing a multiple of line length to the two boundaries.
Example:
For an HD (1080i59) input signal, we have these clean switch regions:
-1 line and -
14.83 μs to 0 line and -14.83 μs;
0 line and -14
.83 μs to 0 line and 14.83 μs;
0 line and 14.83 μs to 1 line and 14.83 μs; etc.
Practical examples:
Example 1:
We have two HD (1080i59) sources, one that indicates an offset of -
10 μs with respect to the
reference (A) and the other an offset of -
20 μs (B). We know that a clean switch region limit is present at -½ line,
which corresponds to -
14.83 μs. We can now determine that this switch will not be clean, because the two
sources are on opposite sides of the limit and are therefore not in the same clean switch region.
Figure 42
Clean Switch Regions Example 1
Example 2:
We have two HD (1080i59) sources, one that indicates an offset of 30 μs with respect to the
reference (A) and the other an offset of 20 μs (B). We know that a clean switch region limit is present at +½ line
-
10μs
-14.83
μs
-
20μs
