Beckhoff KL5101, Документация

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Access from the user program
KL5101 32 Version: 3.1
5.5 Control and status byte
5.5.1 Process data exchange
Control byte for process data exchange
The control byte is transferred from the controller to the terminal. It can be used
• in register mode (REG = 1) or
• in process data exchange (REG = 0).
Various actions are triggered in the KL5101 with the control byte:
Bit 7 6 5 4 3 2 1 0
Name REG=0 - - - EN_Latch_Ex_n Cnt_Set EN_LAT_EXT /
RD_PERIOD
EN_LATC
Bit Name Function
3 En_Latch_Ext
_n The external latch input is activated for the negative edge.
The counter value is stored in the latch register with the first external latch pulse after validity of the
En_Latch_Ext_n bit. When this bit is set, the subsequent pulses do not have any effect on the latch register.
Attention must be paid to ensuring that the corresponding latch valid bit (Latch_Ext_Val) has been removed
from the terminal before alerting of the zero pulse. This functionality can be set in the
feature register [
}
30]
(default setting).
2 Cnt_Set A rising edge at Cnt_Set will set the counter to the value specified in the process data.
1 En_Latch_Ext The external latch input is activated for the positive edge.
The counter value is stored in the latch register with the first external latch pulse after validity of the
En_Latch_Ext bit. When this bit is set, the subsequent pulses do not have any effect on the latch register.
Attention must be paid to ensuring that the corresponding latch valid bit (Latch_Ext_Val) has been removed
from the terminal before alerting of the zero pulse. This functionality can be set in the
feature register [
}
30]
(default setting).
RD_Period The periods between two positive edges at input A are measured with a resolution of 200 ns. When the bit
is set, this period is output in data bytes D2, D3 and D4. This functionality can be set in the
feature register
[ } 30] .
0 En_Latch The zero point latch (C input) is activated.
The counter value is stored in the latch register with the first external latch pulse after validity of the
En_Latch bit (this has priority over En_Latch_Ext). When this bit is set, the subsequent pulses do not have
any effect on the latch register.
Attention must be paid to ensuring that the corresponding latch valid bit (Latch_Val) has been removed from
the terminal before alerting of the zero pulse. (the Latch_Val bit cannot be removed from the terminal until
the C pulse has a low level).
For the external latch input:
Activation of the positive edge (En_Latch_Ext = 1) has priority over activation of the negative edge
(En_Latch_Ext_N = 1).