SC01/SC02/SC11/SC12
IPC GmbH
Sc12hw09.doc
page 10 of 37
24.11.1999 V0.9
TF/WB
4.8 DMA
Pin Name Type Function
DRQ[0..1] I
DMA Request (input, synchronous, level-sensitive)
These pins indicate to the microcontroller that an external device
is ready for DMA channel 0 or 1 to perform a transfer. DRQ0 is
edge-triggered and internally synchronized. DRQ is not latched
and must remain active until serviced.
4.9 Synchronous Peripheral Interface (SPI)
Pin Name Type Function
MEN O
Not implemented yet
MSCK O
Not implemented yet
MISO I
Not implemented yet
MOSI O
Not implemented yet
4.10 I
2
C-Bus
Pin Name Type Function
I
2
CCLK O
I
2
C-Bus Clock (output)
This pin provides clock to an external I
2
C slave.
I
2
CDAT I/O
I
2
C-Bus Data in/out (input/output)
This pin acts either as data input or data output. The IPC@CHIP
family microntroller handles up to 127 external slaves. Itself is
always master and cannot addressed as slave.
4.11 Reset, Power Fail Generator
Pin Name Type Function
RESET# I/O
Reset (input/output, asynchronous, level-sensitive)
If voltage on this pin goes down below 0.8V this pin requires the
microcontroller to perform a reset. When RESET is asserted, the
microcontroller immediately terminates its present activity, clears it’s
internal logic, and transfers CPU control to the reset address,
FFFF0h.
If Vcc goes down below 4.5V or internal watchdog is released this
pin will be driven to GND.
NMI I
Nonmaskable Interrupt (input, synchronous, edge-sensitive)
If voltage on this pin goes down below 1.5V it indicates to the
microcontroller that an interrupt request has occurred. The NMI
signal is the highest priority hardware interrupt and, unlike the
INT6–INT0 pins, cannot be masked. The microcontroller always
transfers program execution to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt vector
table when NMI is asserted.
Although NMI is the highest priority interrupt source, it does not
participate in the priority resolution process of the maskable
interrupts. There is no bit associated with NMI in the interrupt in-
service or interrupt request registers. This means that a new NMI
request can interrupt an executing NMI interrupt service routine. As
