BeagleBone LCD7 Cape
System Reference Manual
Revision A3
Page 20 of 27
5.2
LCD Interface
5.2.1
Expansion connectors
The LCD interface of the BeagleBone LCD7 Cape uses 16 data and 4 control signals
from the BeagleBone’s expansion connectors. By using only 16 signals for LCD_DATA,
more pins can be available at the expansion header for other capes. The quality of 16-bit
LCD output, nonetheless, is very similar to 24-bit. The 4 control signals are horizontal
sync (LCD_HSYNC), vertical sync (LCD_VSYNC), enable input (LCD_EN), and the
pixel clock (LCD_PCLK). Figure 5 shows these LCD signals at expansion connector J1.
Figure 5.
LCD Signals at expansion connector J1
5.2.2
Non-Inverting Bus Transceiver
The LCD signals are buffered through U1 (74AVC32T245), which is a 32-bit dual-
supply bus transceiver. 74AVC32T245 features two ports, A and B. Each port tracks a
separate power-supply rail. This allows for universal low-voltage translation. The output-
enable (OE) input specifies whether the buses are isolated. The direction-control input, on
the other hand, determines the data transmission direction. On the BeagleBone LCD7
Cape, no voltage translation required since its two power rails are both 3.3V. Both the
direction-control and output-enable inputs are set low, so the data are transmitted from B
