22
FUNCTIONAL ARCHITECTURE
jumpers settings required for the memory size, which is automatically
detected by the system BIOS.
The DIMMs are rated 66 MHz (Klamath) or 100 MHz (Deschutes) SDRAM
(Synchronous DRAM). DIMM modules must be ‘Unbuffered’ and operate at
3.3V. All the allowable memory size configurations are described on table
2.1 (Refer to Table 3.6 in the “Configuration” section for the different
combinations and sizes of DIMMs).
Table 2.1. DRAM memory configurations in
Megabytes.
8
16
24
32
40
48
64
72
80
96
128
136
144
176
192
256
2.2.2.
DRAM (DIMM) Sockets
Connection to the main system DRAM can be done via two (2) DIMM
connectors on the system PWA.
Reference: DIMM0, DIMM1
Connector Type: female, 168 pin DIMM, in-line connector
Connector Part Number: Berg. 91145-60024 (Or equivalent)
2.2.3.
System BIOS
The system and video BIOS are stored in a 2M-bit (256Kx8) Flash Memory
device. The system BIOS is always shadowed and cached.
2.3.
L2 Cache Subsystem
The Pentium
II processor cartridge provides an unified 0KB or 512KB
second level (L2) cache to complement the level one data and instruction
(L1) internal caches. The L2 cache is Direct-Mapped non-sectored,
supporting the Write Back policy architecture.
Table 2.2. L2 Cache latency with Burst SRAM
Cycle Type
Clock Count
Burst Read
X-1-1-1
Burst Write (Write-back)
X-1-1-1
Single Read
X
Single Write
X
Pipelined Back-to-Back Burst X-1-1-1,1-1-1-1
1
