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INTRODUCTION
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DIMM sockets can be populated in any order.
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The DRAM Timing register, which provides the DRAM speed grade
control for the entire memory array, will be programmed to use the
timings of the slowest DRAMs installed.
1.1.4.
Data Integrity Subsystem
Several data integrity features are included in the system. These are 64-bit
DRAM interface for EX chipset, parity generation and checking on the PCI
Bus and A.G.P. (for PCI transactions).
PCI Bus.
The system implements parity generation/checking as defined by the PCI
specification.
A.G.P. Bus.
For the operations on the A.G.P. interface using PCI protocol, the system
supports Parity generation/checking as defined by the PCI specification.
Main Memory DRAM Protection Modes.
The system supports three modes of data protection of the DRAM array:
Non-ECC with Byte-Wise Write Support (Default mode, in this mode there is
no provision for protecting the integrity of data in the DRAM array.)
1.1.5.
A.G.P. Interface
The A.G.P. is a high performance, component level interconnect targeted at
3D graphics applications and is based on a set of performance
enhancements to PCI. The IN440EX-D is designed to support the A.G.P.
Interface.
The A.G.P. implementation is compatible with the Accelerated Graphics Port
Specification. The system supports only a synchronous A.G.P. interface
coupling to the host bus frequency. The actual bandwidth will be limited by
the capability of the system’s memory, reaching the highest performance
with fast SDRAM. The A.G.P. Interface supports PCI operations as defined
by the PCI specification. Electrically, only 66MHz PCI operations are
supported.
For the definition of A.G.P. Interface functionality (protocols, rules and
signalling mechanisms, as well as the platform aspect of A.G.P.
functionality), refer to the latest A.G.P. Interface Specification. This
