BBK DV985S, Руководство по обслуживанию, Страница: 36 / 68

SiI
164
PanelLink
Transmitter
Data Sheet
Figure 6. Input Data Setup/Hold Time to IDCK
Figure 7. VSYNC, HSYNC and CTL[3:1] Delay Time from DE
DE
T
LDE
T
HDE
0.8 V
2.0 V
0.8 V
2.0 V
Figure 8. DE High and Low Times
Figure 9. I
2
C Data Valid Delay (driving Read Cycle data)
D[23:0], DE,
HSYNC,VSYNC
IDCK
T
SIDF
T
HIDF
T
SIDR
T
HIDR
50 %
50 % 50 %
50 %
T
DDR
T
DDF
DE
VSYNC, HSYNC,
CTL[3:1]
0.8 V
0.8 V
0.8 V
0.8 V
DE
VSYNC, HSYNC,
CTL[3:1]
SCL
TI2
I2CDVD
SDA