Basler Vision Technologies A202k, Руководство пользователя

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Camera Interface
BASLER A202
k
2-7
DRAFT
2.5 Output Signals
The camera’s output signals include a pixel clock, video data, and video data qualifiers such as
frame valid and line valid. An integrate enabled output signal is also available. Sections
2.5.1
through 2.5.5 describe the output signals.
2.5.1 Pixel Clock
As shown in Figure 2-3 and in Table 2-3 , the pixel clock is assigned to the TxClkIn (transmit clock)
pin of the Camera Link transmitter. The pixel clock is used to time the sampling and transmission
of pixel data as shown in Figures
2-4 and 2-5 . The transmitter used in
A202
k
cameras requires
pixel data to be sampled and transmitted on the falling edge of the clock.
The frequency of the pixel clock is normally 40 MHz. However, when horizontal or full binning is
enabled, the pixel clock is 20 MHz.
2.5.2 Frame Valid Bit
As shown in Figures 2-4 and 2-5 , the frame valid bit indicates that a valid frame is being
transmitted.
2.5.3 Line Valid Bit
As shown in Figures 2-4 and 2-5 , the line valid bit indicates that a valid line is being transmitted.
Pixel data is only valid when the frame valid bit and the line valid bit are both high.
L
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.