Barrett 900 Series, Техническое руководство

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BARRETT 900 SERIES TRANSCEIVERS
4.1.7 Selcall (if enabled)
Australian Standard Selcall format(Codan compatible)
CCIR 493-4 International Standard format:-
Note:-
4.1.8 Audio mute
The selective system utilises Frequency Shift Keying (FSK) as the modulation technique. The design of the
encoder/decoder allows individual channels to be set for operation on either the Australian Standard Selcall
format(Codan comaptible, based on CCIR 493-4) or the true CCIR493-4 format and its associated tones.
Tones used are as follows:-
:-
High tone:- 1870 Hz Low tone:- 1700 Hz Centre tone:- 1785 Hz
High tone:- 1785 Hz Low tone:- 1615 Hz Centre tone:- 1700 Hz
Selcall (and other on air status tones) are generated by the microprocessor U1 and output on pins 26 (SEL
TX DATA1) and 27 (SEL TX DATA2). Transistors Q21 and Q22 combine the signals as necessary and this
signal is output to the RF/Audio PCB to be fed into the transmitted audio path.
Received Selcall signals are filtered by dual bandpass filter U41 A and B. The bandpass filters have
sufficient bandwidth to accommodate both tone sets as above. The audio from the filter output is fed into
the input of the FSK decoder chip XR2211, U27. The VCO within U27 is automatically set to the centre
frequency of the required selcall format. Calibration is performed each time the transceiver is powered up.
This is achieved by routing a single tone (Sel TX data 2) via U43 to the input bandpass filter and
subsequently to the FSK decoder U27. The tone is set to one of the centre frequencies referred to above.
Whilst injecting the tone the calibrating voltage PWR ADJ (see note below), generated by the DAC U38 and
buffered by U10, is varied until the voltage 2211 REF(TP40) and voltage FSK SET V, measured by the
microprocessor on analogue to digital inputs AN6 (U1 Pin 43) and AN5 (U1 Pin 42), are equal. At this point
the FSK centre frequency is set to that of the injected tone.
The signal PWR ADJ referred to above is the calibrating voltage for the selcall phase lock in receive
but changes to the PA ALC power adjustment control in transmit.
When FSK signals are detected the lock detect (U27 pin 6) on the FSK decoder goes high. This causes the
output of the comparator (U27 pin 7) to also go high, reverse biasing D31 and thus causing data to be output
by U42:B. The presence of data (SEL RX DATA) on the microprocessor (U1 pins 24and 25) causes an
interrupt and the subsequent processing of the digital selcall data by the microprocessor.
The Rx audio from the Audio / IF PCB is fed into U34:A which operates as a squaring amplifier. The squared
audio then feeds a charge pump consisting of D40, Q24 and surrounding components. this produces a DC
voltage which is proportional to the frequency of the audio (i.e. voltage rises as frequency increases).
IC33:B acts as a low pass filter with a cut-off frequency of approximately 10 Hz. The output from IC33:B is a
DC voltage which varies at the syllabic rate of the speech received. The absolute output level is also
proportional to the frequency content of the incoming signal as described above.
IC34:C and IC34:D make up a window comparator. The window width is adjusted by the mute sensitivity pot
VR2. The divider network R119 and R120 together with C190, averages the output of IC33:B to provide the
reference voltage for the window comparator. If the output from IC33:B rises or falls below this reference by
the amount set by VR2, then the open collector outputs of IC34:C and IC34:D will discharge C191 and apply
a low to the input of comparator IC34:B pin 6.
The second input of comparator, IC34:B, pin 7 is set to approx. 4 volts by resistor divider R123 and R124.
When input pin 6 falls below 4 volts, the comparator output, pin 1 goes high, this signal, MUTE STATE, is the
indication to the microprocessor that speech has been detected and, if the audio mute is selected, the mute
should be opened. The signal used to control the actual audio mute gate from the microprocessor is RX
MUTE which comes from U1 Pin 6. MUTE STATE is input to the microprocessor U1 on pin14.
When receiving no signal, the mute is held closed by noise coming from both the antenna and that
generated internally by the receiver. This noise has considerable high frequency content, which causes
sufficient output from charge pump mentioned above to hold the mute closed.
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