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21
7
Cyclical transmission
Details: Module
status area
Register
Slave
Master
Register
Master
Slave
RWrm00
h
.b0
Reserved
RWwm00
h
.b0
Reserved
RWrm00
h
.b1
RWwm00
h
.b1
RWrm00
h
.b2
RWwm00
h
.b2
RWrm00
h
.b3
RWwm00
h
.b3
RWrm00
h
.b4
RWwm00
h
.b4
RWrm00
h
.b5
RWwm00
h
.b5
RWrm00
h
.b6
RWwm00
h
.b6
RWrm00
h
.b7
RWwm00
h
.b7
RWrm00
h
.b8
Initial processing
request
RWwm00
h
.b8
Initial processing
completion
RWrm00
h
.b9
Operation condition
setting active
RWwm00
h
.b9
Operation condition
setting request
RWrm00
h
.b10
Error status
RWwm00
h
.b10
Error clear request
RWrm00
h
.b11
Station Ready
RWwm00
h
.b11
Reserved
RWrm00
h
.b12
Warning status
RWwm00
h
.b12
Warning clear request
RWrm00
h
.b13
Reserved
RWwm00
h
.b13
Reserved
RWrm00
h
.b14
RWwm00
h
.b14
RWrm00
h
.b15
RWwm00
h
.b15
Process data
representation
(Byte Swap)
The process data representation is configured using the Byte Swap option. This is configurable
for each IO-Link channel individually and is enabled (1) or disabled (0) using bits RY(m+1)00
h
-
RY(m+1)07
h
. The option applies to both input and output data.
With Byte Swap enabled the process data image looks as follows
(Example for output data):
Word Address
High Byte
Low Byte
RWwm00
h
IOL PD Byte 0
IOL PD Byte 1
RWwm01
h
IOL PD Byte 2
IOL PD Byte 3
RWwm02
h
IOL PD Byte 4
IOL PD Byte 5
…
…
…
If Byte Swap is disabled, the process data are represented as follows:
Word Address
High Byte
Low Byte
RWwm00
h
IOL PD Byte 1
IOL PD Byte 0
RWwm01
h
IOL PD Byte 3
IOL PD Byte 2
RWwm02
h
IOL PD Byte 5
IOL PD Byte 4
…
…
…