AZZA PT-5IVL, Руководство по эксплуатации

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PT-5IVL
SYSTEM BOARD
AWARD BIOS SETUP
5.6 CHIPSET FEATURES SETUP
ROM PCI / ISA BIOS (2A59GXXX)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration : Enabled
DRAM Timing : 70 ns
DRAM RAS# Precharge Time : 4
DRAM R/W Leadoff Timing
: 6
Fast RAS To CAS Delay : 3
DRAM Read Burst (EDO/FP) : x333/x444
DRAM Write Burst Timing : x333
Fast NA to RAS# Delay CLK : 1
Fast EDO Path Select
: Disabled
Refresh RAS# Assertion : 5 CLKs
ISA Clock : PCICLK/4
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Disabled
8 Bit I/O Recovery Time : 1 ESC : Quit
↑↓→←
: Select Item
16 Bit I/O Recovery Time : 1 F1 : Help
PU/PD/+/- : Modify
Memory Hole At 15M-16M : Disabled F5 : Old Values (Shift)F2 : Color
Peer Concurrency : Enabled F6 : Load BIOS Default
F7 : Load Setup Default
Fig. 5-5 CHIPSET FEATURES SETUP screen.
WARNING : The CHIPSET FEATURES SETUP in this screen are provided so that technical
professionals can modify the Chipset to suit their requirement. If you are not a
technical engineer, do not use this program !
Auto Configuration :
When "Enabled", this parameter automatically enters and locks some of the optimum values for the chipset and
CPU. Otherwise, this parameter allows the values of these parameters could be changed.
DRAM Timing :
When "Auto Configuration" is "Enabled", this parameter provides two suit of the optimum values for the chipset
and CPU, depends on the DRAMs' speed, you can select "70 ns" or "60 ns", but the first value maybe caused
your system more stable.
5-5