AZZA KT133BL, Руководство пользователя

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On-Chip Sound
This item allows you to control the onboard AC 97 audio.
On-Chip Modem
This item allows you to control the onboard MC 97 Modem.
4
4
-
-
1
1
2
2
B
B
B
I
I
I
O
O
O
S
S
S
S
S
S
e
e
e
t
t
t
u
u
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p
p
p
CPU to PCI Write buffer
When this field is enabled, writes from the CPU to the PCI bus are buffered, to
compensate for the speed differences between the CPU and the PCI bus. When disabled,
the writes are not buffered and the CPU must wait until the write is complete before
starting another writes cycle.
PCI Dynamic Bursting
When enabled, every write transaction goes to the write buffer. Burstable transactions
then burst on the PCI bus and non-burstable transactions don’t.
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1.
PCI#2 Access #1 Retry
When disabled, PCI#2 will not be disconnected until access finishes (default). When
enabled, PCI#2 will be disconnected if max retries are attempted without success.
AGP Master 1 WS Write
When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with one-wait
states.
AGP Master 1 WS Read