AZZA KT133BL, Руководство пользователя

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conventional ISA bus and the PCI bus. The default settings have been chosen because
they provide the best operating conditions for your system. So please do not change the
default setting unless you have sound technical background.
DRAM Timing By SPD
When enabled, the system BIOS will read the DRAM parameters from the SPD (Special
Presence Detect) chip on the DIMM module and set the DRAM timing automatically.
DRAM Clock
This field allows you to select the DRAM access speed to control the memory
performance.
DRAM Cycle Length
This setting defines the CAS timing parameter of the SDRAM in term of clock, to The
default value is 3.
BANK Interleave
This field allows you to select how many bank of DRAM is installed on the mainboard so
that the system BIOS will be able to adjust the SDRAM interleave access mode to optimize
the SDRAM performance.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this
area of system memory usually discusses their memory requirements.
n
Enabled: The memory space between 15 ~ 16MB will be remapped for ISA cards.
n
Disabled: No memory will be remapped.
4
4
-
-
1
1
0
0
B
B
B
I
I
I
O
O
O
S
S
S
S
S
S
e
e
e
t
t
t
u
u
u
p
p
p
PCI Master Pipeline Req
This field allows you to enable or disable the PCI pipeline access.
P2C/C2P Concurrency
This selection field allows you to enable/disable the PCI to CPU, CPU to PCI concurrency.
Fast R-W Turn Around
This item controls the DRAM timing. It allows you to enable/ disable the fast read/write
turn around.