361 Mainboard Series
361 Mainboard Series
Page
Page 30
30
SDRAM Cycle Length
This setting defines the CAS timing parameter of the SDRAM in terms of clock. The default
value is 3. We recommend that you leave the default value.
Bank Interleave
This field allows you to select how many banks of DRAM are installed on the mainboard so
that the system BIOS will be able to adjust the SDRAM interleave access mode to optimize the
SDRAM performance.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is reserved,
it cannot be cached. The user information of peripherals that need to use this area of system
memory usually discusses their memory requirements.
Enabled:
The memory space between 15~16MB will be remapped for ISA cards.
Disabled:
No memory will be remapped.
PCI Master Pipeline Req
This field allows you to enable or disable the PCI pipeline access.
P2C/C2P Concurrency
This selection field allows you to enable/disable the PCI to CPU, CPU to PCI concurrency.
Fast R-W Turn Around
This item controls the DRAM timing. It allows you to enable/ disable the fast read/write turn
around.
System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM. This results system performance.
However, if any program writes to this memory area, a system error may occur.
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance.
However, if any program writes to this memory area, a system error may occur.
Frame Buffer Size
A frame buffer is the memory region on your graphics card that stores all the information
which is not on the screen. This fields allows you to choose the buffer size.
Managing The PC BIOS
Managing The PC BIOS
PC BIOSPC BIOS
VIA_361_Manual_030701_Re...
page 30
Wednesday, July 11, 2001 13:37
Composite
