Axiom SBC8156, Руководство пользователя

Страница: 55 / 96

SBC8156 Pentium All-in-One CPU Card Series User’s Manual
Award BIOS Utility
&,
z
DRAM Leadoff Timing
Selects the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Changing the
value from the setting determined by the board designer for the
installed DRAM might cause memory errors. The default value is
“10/6/3” .
z DRAM Read Burst (EDO/FP)
Sets the timing for reads from EDO (Extended Data Output) or FPM
(Fast Page Mode) memory. The lower the timing numbers, the faster
the system addresses memory. Selecting timing numbers lower than
the installed DRAM specifications may result in memory errors. The
default value is
“x222/x333” .
z
DRAM Write Burst Timing
Sets the timing for writes to memory. The lower the timing numbers,
the faster the system addresses memory. Selecting timing numbers
lower than the installed DRAM specifications may result in memory
errors. The default value is
“x222” .
z Fast EDO Lead Off
Set this option to Enabled only when using EDO DRAMs in either a
synchronous cache or a cache-less system. It causes a 1-HCLK pull-in
for all read leadoff latencies for EDO DRAMs (i.e., page hits, page
misses, and row misses). Select Disabled if any of the DRAM rows is
populated with FPM DRAMs. The default value is “Disabled” .
z
Refresh RAS# Assertion
This item selects the number of clock ticks RAS# (Row Address Strobe)
is asserted for refresh cycles. The default value is “4 Clks” .
z Fast RAS to CAS Delay
When DRAM is refreshed, both rows and columns are addressed
separately. This field lets you insert a timing delay between the CAS
and RAS strobe signals used when DRAM is written to, read from, or
refreshed. The default value is “3” .
z DRAM Page Idle Timer
Selects the amount of time in HCLKs that the DRAM controller waits to
close a DRAM page after the CPU becomes idle. The default value is
“2 Clks”
.