MC13192U Transceiver Module
User Guide
6
Module Option Jumpers
JP1 - Select Signal Option
JP1 provides the Serial Peripheral Interface (SPI) device select signal option on the J1
connector. Two select signals maybe optioned incase the default connection is in use
by another peripheral. The SMAC software example will need to be configured to apply
the secondary signal. See the connection charts for the host controller to determine the
signal applied.
Position 1-2 (default):
Enables the host MCU SPI port SS* signal or J1 pin 23 as the
MC13192U select signal.
Position 2-3:
Enables the host MCU secondary select signal or J1 pin 24 as the
MC13192U select signal. See the connection charts to determine signal name applied
for particular host MCU.
JP2 – Clock-Out Enable Option
JP2 enables the MC13192 device optional clock output signal to connector J2 pin 14.
The clock output signal is not applied to the default application connector J1. See the
MC13192 device user guide and the SMAC software example for configuration of the
clock output signal if required.
J1 Connector – Default Host I/O Connection
J1 is the default application interface connector and it provides all power,
communication and status signals between the module and the host controller.
Connector organization is for a compatible installation in the Freescale DEMO series or
SLK series boards, and the Axiom CSM series. User should verify compatibility by
referring to the MC13192U Host controller signal chart.
Signal Name
J1 Pin
Signal Name
VDD (3.3 - 5)
1
2
IRQ_OUT*
GND (vss)
3
4
x
x
5
6
x
x
7
8
x
IDLE (GPIO1)
9
10
x
V_CRC (GPIO2)
11
12
x
RESET_IN*
13
14
x
ATTN_IN*
15
16
x
SIN
17
18
x
SOUT
19
20
RXTXEN
SCK
21
22
ANTCTL
(JP1 1-2) SEL1*
23
24
SEL2* (JP1 2-3)
Notes:
1) Signal names refer to the MC13192U operation.
2)
The ‘*’ symbol indicates low active signal.
