CMD-5xx 08/07/02
10
Synchronous SRAM Memory
The synchronous SRAM Memory Bank is composed of four 256K x 32 memory devices. These memory devices are connected in
linear order from U2 to U5 so that the low order address of the memory bank will access U2 and the high order addresses of the
memory bank will access U5. This memory bank must be configured as a 32 bit wide port but is byte, half word, and word
accessible for read or write operations. The synchronous SRAM memory on revision C and earlier boards (CY1339) requires 1 wait
state no matter the bus clock frequency to operate in asynchronous mode and will provide 32-bit wide burstable output of 2/1/1
cycles type. Revision D boards provide 0 wait state SRAM memory (CY1338) and will operate a 1/1/1 burst cycle.
Burstable Flash Memory
The Burstable Flash Memory Banks U13 and U14 contain two Intel DT28F160F3 or AMD AM29BL162B type flash devices. The
two flash devices are configured in parallel to provide either a 16 bit wide port operating U13 or a 32 bit wide port operating both
U13 and U14. Both devices require wait states when accessed in asynchronous mode and the same wait state delay during the first
cycle of a burst type access. Refer to the specific device data sheet and sample software provided for configuring the flash memory.
Port Replacement Unit (PRU) Memory
The Port Replacement Unit (PRU) provides for single chip operation of the MPC5xx I/O ports used for address, data, and interrupts
during 32 bit bus operation. The PRU also provides memory mapping and control of the LCD and Keypad Ports. The PRU_EN
jumper must be installed (see PRU_EN section) and chip select configuration for the PRU must be set to 32 bits wide and should
provide external access termination (use TA* signal) for correct operation of all functions.
The I/O ports provided by the PRU do not duplicate signal levels or internal pull-up operation of the MPC5xx I/O ports. The PRU
I/O port output voltage levels are limited to +3.3V high while the MPC5xx I/O ports typically will provide voltage level of +5V high
(refer to MPC5xx technical data for host). PRU I/O port input voltage levels are tolerant of +5V signals. The PRU register
operation and memory map closely follows the MPC5xx I/O port data and direction registers located at internal addresses 2FC024 –
2FC02F. Following is the memory map of the PRU.
PRU Offset
Address
Register Name
Register Information
Port
0x0000
LCD CMD1
LCD Module address 0, Command register access. Bits D0 – 7 of 32
LCD_PORT
1
0x0004
LCD DATA1
LCD Module address 1, Display Data register access. Bits D0 – 7 of 32.
LCD_PORT
1
0x0008
LCD CMD2
LCD Module address 2, Command register access. Bits D0 – 7 of 32.
LCD_PORT
1
0x000C
LCD DATA2
LCD Module address 3, Display Data register access. Bits D0 – 7 of 32.
LCD_PORT
1
0x0010
KEY DATA
Keypad or Keyport data register
KEY_PORT or
KEYPAD
2
0x0014
Reserved
Not applied, access termination provided.
0x0018
Reserved
Not applied, access termination provided.
0x001C
Reserved
Not applied, access termination provided.
0x0020
Reserved
Not applied, access termination provided.
0x0024
PRU Port D
D0-31 I/O port replacement
SGPIODT1
3
0x0028
PRU Port A&C
C0-7, A8-31 I/O port replacement
SGPIODT2
3
0x002C
PRU Port Direction
Replacement Port Direction
SGPIOCR
3
1. Refer to LCD Module data sheet for register information.
2. Key_Port or Keypad is read only and writes have no effect. Keypad data is provided in a binary number in bits D0 – D4 for
current or last key pressed while bit D7 indicates if the key is currently active (pressed).
3. Refer to MPC5xx users manual for register operation.
MEM Sockets Memory
The primary function of the MEM sockets memory bank is for CMD-5xx firmware. This memory bank is the default program code
source from Reset or Power on and can only be enabled to operate from chip select CS0. The two memory sockets U15A and U16
provide a 16 bit wide port (default) while memory socket U15B provides an optional 8 bit wide port. If the 8 bit wide port is used
the U16 socket should be vacant of any memory device for proper operation. The MEM sockets are configured for standard 8 bit
wide 27xxx series EPROM’s from 32K bytes up to 1M byte per socket. These devices require wait states during access for proper
operation.
