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Innovator CHV400BTD ATSC Transmitter
Board Descriptions
Technical Manual, Rev. 0
64
ASI to 310 Conversion Board, SFN (1309764)
The ASI signal is input to the ASI to S310 conversion board via J1. U2 de-serializes the
ASI input signal into a parallel byte stream. The parallel byte stream is clocked into U6
which buffers and converts it to a valid S310 bi-phase encoded signal. For SFN
operation the ASI payload must be 19.392568 Mb/s ±2 ppm. A 38.785317 MHz VCXO
locks to the exact S310 bit-rate using a Digital PLL. This method ensures the extracted
S310 stream is frequency locked without modifying its content i.e. add/drop null
packets, PCR restamp, etc. The final S310 output of the board is at J5.
NOTE:
In your system contains an (Optional) KTECH Receiver Tray, information on the
Tray is contained in the separate manufacturers supplied instruction manual.
Содержание CHV400BTD
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