
BIOS SETUP
28
MI950 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
System BIOS Cacheable
Enabled
ITEM HELP
Memory Hole at 15M-16M
Disabled
Menu Level >
PCI Express Root Port Func
Press Enter
Disable MCHBAR MMIO
Enabled
VT-d Disabled
Intel AMT Configuration
Press Enter
** VGA Setting **
PEG/On Chip VGA Control
Auto
On-Chip Frame Buffer Size
32MB
DVMT Mode
Enabled
DVMT/FIXED memory Size
256MB
PAVP Mode
Lite
Phoenix - AwardBIOS CMOS Setup Utility
Intel AMT Configuration
AMT BIOS Support
Enabled
ITEM HELP
SOL Support
Enabled
Menu Level >
IDE-R Support
Enabled
Platform Mng Selection
Intel AMT
QST Support
Disabled
Danbury Technology
Disabled
OEM Flag BIT0
Disabled
OEM Flag BIT1
Disabled
OEM Flag BIT2
Disabled
System BIOS Cacheable
The setting of
Enabled
allows caching of the system BIOS ROM at
F000h-FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space below 16 MB. The choices are
Enabled
and
Disabled
.
PCI Express Root Port Func
Press Enter to configure this field.
Disable MCHBAR MMIO
By default, this feature is enabled.
Содержание MI950
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Страница 8: ...INSTALLATIONS Board Dimensions 4 MI950 User s Manual ...
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Страница 60: ...DRIVERS INSTALLATION 8 After the Setup is complete click Exit 56 MI950 User s Manual ...