As before, if the delay is negative, the order of the SYNC and OUT pulses is reversed.
The last figure illustrates the relationship between the signal when an external TTL-
level trigger is used in the PW
IN
=PW
OUT
mode. In this case, the output pulse width
equals the external trigger’s pulse width (approximately), and the delay circuit is
bypassed:
21
SYNC OUT
50 ns, FIXED
MAIN OUTPUT
PULSE WIDTH
DELAY > 0
3V, FIXED
> 4 ns
TTL LEVELS
(0V and 3V-5V)
TRIG
(external input)
PROPAGATION DELAY (FIXED)
AMPLITUDE, VARIABLE
+5V (TTL) or -0.8V (ECL)
0V (TTL) or -1.6V (ECL)
LOGIC OUTPUT
+5V (TTL) or -0.8V (ECL)
0V (TTL) or -1.6V (ECL)
LOGIC OUTPUT
Содержание AV-1030-B
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