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2.2.2
PCI Express x4 Interface
One of the GTX transceiver banks is connected to the PCI Express x4 card edge interface on the Mini-
Module Plus Baseboard 2. PCI Express is an enhancement to the PCI architecture where the parallel
bus has been replaced with a scalable, fully serial interface. The differences in the electrical interface
are transparent to the software so existing PCI software implementations are compatible. Use of the
Zynq 7Z045 Mini-Module Plus Development Board in a PCI Express application requires the
implementation of the PCI Express protocol in the ZYNQ PL. The PCI Express Endpoint Block
embedded in the Zynq 7Z045 implements the PCI Express protocol and the physical layer interface to
the GTX ports. This block must be instantiated in the user design. Refer to UG963 documentation on
the Xilinx website for more details.
The PCI Express electrical interface on the Zynq 7Z045 Mini-Module Plus Development Board
consists of 4 lanes, having unidirectional transmit and receive differential pairs. It supports
second generation PCI Express data rates of 5.0 Gbps. In addition to the data lanes there is a
100 MHz reference clock that is provided from the system slot. In order to work in open
systems, add-in cards must use the reference clock provided over the PCI Express card edge
to be frequency locked with the host system. The 100 MHz clock is sourced from the baseboard
edge connector and forwarded to a jitter attenuator prior to being forwarded to the Zynq Mini-
Module Plus via the JX2 connector.
There is also a side band signal from the PCI Express card edge that connects to a standard
I/O pin on th
e Zynq 7Z045. The “PERST#” signal is an active low reset signal provided by the
host PCI Express slot. The following figure shows the PCI Express interface to the Zynq 7Z045.
Figure 4
– PCI Express x4 Interface
