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4

Practical Connections of the Evaluation Board Using IGBT or SiC/GaN MOSFET for Actual Inverter Test

1.  Solder a IGBT or SiC/GaN MOSFET at Q1(or Q2) for top and bottom arms of the half bridge inverter isolated drivers
2.  Connect a +5V DC isolated supply1 5V and GND terminals of CON1 for both arms of the isolated drivers;
3.  Connect another isolated DC supply2 (voltage range from 15V~30V) across Vcc2a and Veea at pin-7 and pin-5 of IC2a 

respectively for bottom arm

4.  Connect the signal output (meant to drive the bottom arm of half-bridge inverter) from microcontroller to signal 

input 1 across pin IN1+ and IN1- of CON1a of bottom inverter arm isolated driver

5. Connect the signal output (meant to drive the top arm of half-bridge Inverter) from microcontroller to signal  

input 2 across pin IN2+ and IN2- of CON1b of top inverter arm isolated driver;

Note: Signal input 2 should be 180

°

 out of phase with reference to  signal input 1;  Check that Vcc2b (voltage close to Vcc2a) 

is generated through the bootstrap components D3b and R6

6.  Use a multi-channel digital oscilloscope to capture the waveforms at the following points –

a.  LED signal at IN1+ pin with reference to  GND for bottom arm
b.  LED signal at IN2+ pin with reference to  GND for top arm
c.  Vga for the gate driving voltage of Q1a(or Q2a) with reference to  Vea of bottom inverter arm (differential probe 

needed)

d. Vgb for the gate driving voltage of Q1b(or Q2b) with reference to Veb of top inverter arm (differential probe 

needed)

7.  Connect a power cable from output pin (marked Load) to the inverter load
8.  Connect the high voltage cables from top arm SiC/GaN MOSFET drain pin (or IGBT's Collector pin) to HVDC+ and from 

bottom arm SiC/GaN MOSFET source pin (or IGBT's Emitter pin) to HVDC- respectively as shown. 

Note: It is advised to enable the current limiting function of the HV Power Source supplying the High Voltage DC Bus voltage 

during this test to protect the Inverter and its driver circuitries.

Figure 4.  Connection of Evaluation Board in Actual Applications

M

icr

oc

on

tro

lle

r

IN1+
IN1 - Signal Input 1

+5

V

Gn

d

DC

 Su

pp

ly

1

IN2+
IN2 - Signal Input 2

PowerMos

Mounted

PowerMos

Mounted

1

1

2

3

15~30V

+

-

DC Supply2

4

5

15~30V

+

-

5

6a

6b

6c

6d

Load

7

HVDC+

HVDC -

8

8

K1

50

10

1

W349

W349

06JAN15

06JAN15

Содержание ACPL-P349

Страница 1: ...negative supply is not needed Note If negative supply is needed S2 S3 jumpers need to be removed 4 Bootstrap Diode D3b and Resistor R6 are connected by default These 2 components are provided to help...

Страница 2: ...enerator across IN1 IN1 pins of CON1a to simulate microcontroller output to drive lower arm of the half bridge Inverter b Another 10kHz 5V DC pulse at 180 out of phase to 4a from the dual output signa...

Страница 3: ...LEDa LEDa Vcc1a Gnda LEDb LEDb Vcc1b Gndb 0 1 F 0 1 F SS32 SS32 BYM26F 10 F Ta R05P15D R8 1 2 5 6 7 1 2 5 6 7 10 F Ta 10 F Ta TP2b TP3b TP4b TP1b TP2a TP3a TP4a TP1a S1a S2a S1b S2b CON1a CON1b IC1a...

Страница 4: ...nts D3b and R6 6 Use a multi channel digital oscilloscope to capture the waveforms at the following points a LED signal at IN1 pin with reference to GND for bottom arm b LED signal at IN2 pin with ref...

Страница 5: ...ure 5 accommodates 2 ACPL P349 ACPL W349 IC s Therefore each board is capable of driving top and bottom arms of the half bridge Inverter It allows the designer to test the performance of the gate driv...

Страница 6: ...lamping voltage Descriptions of each of the 7 different power supply schemes are provided below Users are encouraged to evaluate all seven schemes to decide which one is most suitable for his her need...

Страница 7: ...of negative Vee at Veea Veeb Therefore all S2 s must be open while all S3 s must be shorted Power scheme 7 This scheme is useful if dual output 15V DC DC converters are not available or dual output 9...

Страница 8: ...effects of D2 and the gate capacitance of Q1 To improve the turn off speed the board is equipped with diode resistor pair footprints at D1 and R5 not mounted NM to increase the gate current during tur...

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