SAM E70 Pin
Exthernet Function
Shared With
PD7
PHY_RXER
PD8
PHY_MDC
PD9
PHY_MDIO
–
PC10
PHY_RESET
–
PA14
PHY_INTERRUPT
–
The KSZ8081RNACA also has a set of parameters that are latched in during reset based on I/O pin
levels. These configuration options have a default mode on the kit done by external pull-up and pull-down
resistors. For detailed information about the configuration, refer to the
.
Table 4-20 KSZ8081RNACA Configuration
Configuration Name Default Value on
Kit
Default Configuration
PHYAD
0x0h
The PHYs address is 0x0h. It can be set to 0x3h if R70
and R71 are permutted.
AUTONEG
Pull-Up
Auto negotiation enabled and set 100Mbps speed
4.4.7.
AT24MAC402
The SAME70-XPLD features one Atmel AT24MAC402 serial EEPROM with an EIA-48 MAC address
connected to the SAM E70 through I
2
C. This AT24MAC402 is configured on the I
2
C interface with the
address 0x37h. It contains a MAC address for use with the Ethernet interface.
on page 36 lists all I/O lines connected to the AT24MAC402 device.
Figure 4-26 AT24MAC402 Schematic
MAC24_A0
MAC24_A1
MAC24_A2
TWD0
TWCK0
VCC_3V3
VCC_3V3
PA3
PA4
PC11
R603
10K
U600
AT24MAC402-MAHM-T
A0
1
A1
2
A2
3
GND
4
SDA
5
SCL
6
WP
7
VCC
8
R600
10K
R601
10K
R602
10K
C600
100nF
Table 4-21 AT24MAC402 Connections
SAM E70 Pin Function AT24MAC402 Function Shared With
PA3
TWD0
SDA (Serial Data Line)
,
PA4
TWCK0
SCL (Serial Click Line)
,
PC11
GPIO
WP (Write Protect)
--
Atmel SAME70-XPLD [USER GUIDE]
Atmel-44050A-SAME70-XPLD_User Guide-12/2015
36
Содержание SAME70-XPLD
Страница 53: ...Figure 6 3 Top Signals Layer Atmel SAME70 XPLD USER GUIDE Atmel 44050A SAME70 XPLD_User Guide 12 2015 53 ...
Страница 54: ...Figure 6 4 Layer 2 Ground Atmel SAME70 XPLD USER GUIDE Atmel 44050A SAME70 XPLD_User Guide 12 2015 54 ...
Страница 55: ...Figure 6 5 Layer 3 Power Planes Atmel SAME70 XPLD USER GUIDE Atmel 44050A SAME70 XPLD_User Guide 12 2015 55 ...
Страница 56: ...Figure 6 6 Bottom Signals Layer Atmel SAME70 XPLD USER GUIDE Atmel 44050A SAME70 XPLD_User Guide 12 2015 56 ...