18
SAMA5D3x-EK User Guide [USER GUIDE]
11180B–ATARM–29-Oct-13
Figure 4-8.
Ronetix DDR2 Memory
One NAND Flash: NAND is connected to the processor. Maximum size is 256 bytes.
One NOR Flash (optional, not populated): NOR Flash is 16 bits wide. Maximum size is 128 Mbytes.
DDR_A3
DDR_A6
DDR_A13
DDR_A12
DDR_A11
DDR_A2
DDR_A1
DDR_A0
DDR_A8
DDR_A5
DDR_A4
DDR_A10
DDR_A7
DDR_A9
DDR_A13
DDR_A11
DDR_A7
DDR_A6
DDR_A8
DDR_A0
DDR_A1
DDR_A4
DDR_A3
DDR_A5
DDR_A10
DDR_A9
DDR_A12
DDR_A2
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D27
DDR_D28
DDR_D31
DDR_D29
DDR_D30
DDR_D15
DDR_D20
DDR_D24
DDR_D22
DDR_D21
DDR_D23
DDR_D19
DDR_D18
DDR_D17
DDR_D16
DDR_D26
DDR_D25
DDR_D9
DDR_D11
DDR_D12
DDR_D4
DDR_D2
DDR_D10
DDR_D8
DDR_D7
DDR_D3
DDR_D6
DDR_D5
DDR_D0
DDR_D1
DDR_D13
DDR_D14
DDR_D1
DDR_D0
DDR_D12
DDR_D2
DDR_D9
DDR_D10
DDR_D11
DDR_D6
DDR_D5
DDR_D4
DDR_D3
DDR_D7
DDR_D8
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D31
DDR_D30
DDR_D24
DDR_D23
DDR_D22
DDR_D21
DDR_D18
DDR_D19
DDR_D20
DDR_D27
DDR_D26
DDR_D29
DDR_D28
DDR_D25
DDR_A[0-13]
DDR_A[0-13]
DDR_A[0-13]
DDR_D[0-31]
DDR_D[0-15]
DDR_D[16-31]
DDR_ADDR
DDR_ADDR
DDR_ADDR
DDR_DATA
DDR_DATA
DDR_DATA
DDR_BA2
5
DDR_BA1
5
DDR_BA0
5
DDR_DQM2
5
DDR_DQS2
5
DDR_DQS3
5
DDR_WE#
5
DDR_CAS#
5
DDR_RAS#
5
DDR_CKE
5
DDR_DQM3
5
DDR_DQM1
5
DDR_DQM0
5
DDR_DQS1
5
DDR_DQS0
5
DDR_CK#
5
DDR_CK
5
DDR_CS#
5
DDR_RAS#
5
DDR_CAS#
5
DDR_WE#
5
DDR_BA0
5
DDR_BA2
5
DDR_BA1
5
DDR_VREF
5
DDR_DQM1
5
DDR_DQM0
5
DDR_BA0
5
DDR_BA1
5
DDR_RAS#
5
DDR_CS#
5
DDR_WE#
5
DDR_CAS#
5
DDR_BA2
5
DDR_CK
5
DDR_CK#
5
DDR_DQS1
5
DDR_DQS0
5
DDR_DQS2
5
DDR_DQS3
5
DDR_DQM3
5
DDR_DQM2
5
DDR_VREF
5
DDR_VREF
5
DDR_VREF
5
DDR_CKE
5
DDR_CKE
5
DDR_CK#
5
DDR_CK
5
DDR_VREF
5
DDR_CS#
5
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L7
BLM15AG121SN1D
C60
100n/10V
C63
100n/10V
C55
100n/10V
C58
100n/10V
C59
100n/10V
C51
100n/10V
C50
100n/10V
C54
100n/10V
C46
100n/10V
C47
100n/10V
C62
100n/10V
C65
100n/10V
C56
100n/10V
C44
100n/10V
C48
100n/10V
C45
100n/10V
C52
100n/10V
C49
100n/10V
C57
100n/10V
C53
100n/10V
C76
100n/10V
C77
100n/10V
C79
100n/10V
C108
100n/10V
C109
100n/10V
C110
100n/10V
C111 100n/10V
C112 100n/10V
C113 100n/10V
C114 100n/10V
C115 100n/10V
C116
100n/10V
C117
100n/10V
C118
100n/10V
C119 100n/10V
C120 100n/10V
C61
100n/10V
C64
4u7/6V3/X5R
B10
C11
A9
D11
B9
E10
D10
A8
C10
B8
F11
A7
D9
A6
H12
H17
H13
G17
G16
H15
F17
G15
F16
E17
G14
E16
D17
C18
D16
C17
B16
B18
C15
A18
C16
C14
D15
B14
A15
A14
E12
A11
B11
F12
A10
E11
G12
E15
B15
D12
E18
G18
B17
B13
D18
F18
A17
A13
C8
B12
A12
B7
G11
A5
B5
E9
B6
F9
C12
E13
C13
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQSN0
DDR_DQSN1
DDR_DQSN2
DDR_DQSN3
DDR_CS
DDR_CLK
DDR_CLKN
DDR_CKE
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CALN
DDR_CALP
DDR_VREF
U3-H
SAMA5D3x
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
L3
L1
K3
L7
K7
L8
K9
K2
J8
K8
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
F7
E8
B7
A8
F3
B3
A2
E2
J2
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU(A13)
RFU
RFU
BA0
BA1
BA2
WE#
CAS#
RAS#
CS#
ODT
CKE
CK
CK#
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS#/NU
UDQS
UDQS#/NU
LDM
UDM
NC
NC
VREF
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
U4
MT47H128M16RT-3:C
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
L3
L1
K3
L7
K7
L8
K9
K2
J8
K8
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
F7
E8
B7
A8
F3
B3
A2
E2
J2
A1
E1
J9
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RFU(A13)
RFU
RFU
BA0
BA1
BA2
WE#
CAS#
RAS#
CS#
ODT
CKE
CK
CK#
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDQS#/NU
UDQS
UDQS#/NU
LDM
UDM
NC
NC
VREF
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
U5
MT47H128M16RT-3:C
0402
R12
1k5/1%
0402
R14
1k5/1%
0402
R51
0R
0402
R50
0R
DNP
0402
R52
0R
DNP
0402
R53
0R
0402
R11
1R
0402
R72
4k7
0402
R73
4k7
0402
R70
4k7
0402
R71
4k7
0402
R13
200R
0402
R10
200R
TP13
TP12
12.09.2012
group 1AB
group 1AB
A
top/bot
Differential
100 ohms
top/bot
top/bot
group 1AB
group 1AB
group 1AB
group 1AB
group 1AB
Zo=50 ohm
s
keepi
ng pr
opagat
io
n del
a
y equal
(b
et
w
e
en 2A &
2B t
oo)
DQS-
4
w
-D
Q-
3
w
-D
QM-
4
w-
DQS
group 2B
L3 & L8
D
at
a t
races m
ay not
exceed 1.
3 i
nches (
33.
0 m
m
).
D
a
ta
tra
c
e
s
m
u
s
t b
e
le
n
g
th
-m
a
tc
h
e
d
to
w
ith
in
0
.1
in
c
h
(2
.5
4
m
m
).
D
at
a t
races m
ust
m
at
c
h t
he dat
a gr
oup t
race l
engt
hs t
o w
it
hi
n
0.
25 i
nches (
6.
35 m
m
).
DQS-
4
w
-D
Q-
3
w
-D
QM-
4
w-
DQS
Zo=50 ohm
s
keepi
ng pr
opagat
io
n del
a
y equal
(b
et
w
e
en 2A & 2B t
oo)
L3 & L8
group 2A
minimizing crosstalk with [DQ, DQS, DQM]
Zo=50 ohms
B
Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA.
The layout EBI DDR2 should use controlled impedance traces of ZO = 50Ohm characteristic impedance.
Trace width = 0.13mm: target 50Ohm impedance.
Trace space = 0.30 to 0.38 mm.
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
L3 & L8
group 3AB
Chenged U4 and U5
From MT47H64M16HR-25H to MT47H128M16RT-3:C
