Atmel SAM4S Series, Предварительный информационный лист

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
17.4 Supply Controller Functional Description
17.4.1 Supply Controller Overview
The device can be divided into two power supply areas:
• The VDDIO Power Supply: including the Supply Controller, a part of the Reset Controller, the
Slow Clock switch, the General Purpose Backup Registers, the Supply Monitor and the Clock
which includes the Real Time Timer and the Real Time Clock
• The Core Power Supply: including the other part of the Reset Controller, the Brownout
Detector, the Processor, the SRAM memory, the FLASH memory and the Peripherals
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC
intervenes when the VDDIO power supply rises (when the system is starting) or when the
Backup Low Power Mode is entered.
The SUPC also integrates the Slow Clock generator which is based on a 32 kHz crystal oscilla-
tor and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the
software can enable the crystal oscillator and select it as the Slow Clock source.
The Supply Controller and the VDDIO power supply have a reset circuitry based on a zero-
power power-on reset cell. The zero-power power-on reset allows the SUPC to start properly as
soon as the VDDIO voltage becomes valid.
At startup of the system, once the voltage VDDIO is valid and the embedded 32 kHz RC oscilla-
tor is stabilized, the SUPC starts up the core by sequentially enabling the internal Voltage
Regulator, waiting that the core voltage VDDCORE is valid, then releasing the reset signal of the
core “vddcore_nreset” signal.
Once the system has started, the user can program a supply monitor and/or a brownout detec-
tor. If the supply monitor detects a voltage on VDDIO that is too low, the SUPC can assert the
reset signal of the core “vddcore_nreset” signal until VDDIO is valid. Likewise, if the brownout
detector detects a core voltage VDDCORE that is too low, the SUPC can assert the reset signal
“vddcore_nreset” until VDDCORE is valid.
When the Backup Low Power Mode is entered, the SUPC sequentially asserts the reset signal
of the core power supply “vddcore_nreset” and disables the voltage regulator, in order to supply
only the VDDIO power supply. In this mode the current consumption is reduced to a few micro-
amps for Backup part retention. Exit from this mode is possible on multiple wake-up sources
including an event on WKUP pins, or a Clock alarm. To exit this mode, the SUPC operates in the
same way as system startup.