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AVR1612

 

 

5

8282A-AVR-11/10 

PDI instruction usage example: 

  Write a 32-bit address into PDI Controller's pointer 

Pseudo Directive: 

 

ST ptr 0x12345678 

PDIBUS hex code:   

0x6B 0x12 0x34 0x56 0x78 

NOTE 

”0x6B” stands for “ST ptr” command. 

  Write a value to a address with *(ptr++) instruction through the PDI Controller 

Pseudo Directive: 

 

ST *(ptr++) 0xFF 

PDIBUS hex code:   

0x67 0xFF 

NOTE 

”0x67” stands for “ST *(ptr++)” command. 

 Write the repeat number into PDI Controller (REPEAT command uses 

BIG_ENDIAN data) 
Pseudo Directive: 

 

REPEAT 0x1234 

PDIBUS hex code:   

0xA1 0x34 0x12 

NOTE 

”0xA1” stands for “REPEAT” command and 2 bytes data length. 

  Load data from PDIBUS Data Space using indirect addressing 

Pseudo Directive: 

 

LD *(ptr++) 

PDIBUS hex code:   

0x27 

Then read the PDIBUS for the loading data. 

NOTE 

”0x27” stands for “LD *(ptr++)” command. 

Please refer to “29.5.7 Instruction Set Summary” section of thfor more information. 

2.5 NVM Commands 

The NVM commands that can be used for accessing the NVM memories from 
external programming are listed in
 

Table 2-2

. This is a super-set of the commands 

available for self-programming. Each command has to be loaded to the target NVM 
CMD register using the PDI commands. 

For external programming, the Trigger for Action Triggered Commands is to set the 
CMDEX bit in the NVM CTRLA register (CMDEX). The Read Triggered Commands 
are triggered by a direct or indirect Load instruction (LDS or LD) from the PDI (PDI 
Read). The Write Triggered Commands is triggered by a direct or indirect Store 
instruction (STS or ST) from the PDI (PDI Write). 

 

Table 2-2. 

NVM commands available for external programming. 

CMD[6:0] Commands/Operation 

Trigger 

0x00 No 

Operation 

0x40 Chip 

Erase 

(1)

 CMDEX 

0x43 

Read NVM 

PDI Read 

Flash Page Buffer 

0x23 

Load Flash Page Buffer 

PDI Write 

0x26 

Erase Flash Page Buffer 

CMDEX 

Содержание AVR1612

Страница 1: ...NVM Controller trough the PDI interface and executing NVM Controller commands The PDI is a 2 pin interface using the Reset pin for the clock input PDI_CLK and the dedicated pin for data input and out...

Страница 2: ...scribes the PDI serial frame format Figure 2 1 PDI serial frame format 2 2 Serial transmission and reception The PDI physical layer is either in Transmit TX or Receive RX mode of operation By default...

Страница 3: ...1287 ATXmega128A1 XCK RXD TXD 220R 220R PDI CLK PDI DATA 2 4 PDI instruction set The PDI has a small instruction set that is used for all access to the PDI itself and to the internal interfaces All in...

Страница 4: ...D 0x20 Load data from PDIBUS Data Space using indirect addressing ST 0x60 Store data to PDIBUS Data Space using indirect addressing LDCS 0x80 Load data from PDI Control and Status Register Space STCS...

Страница 5: ...refer to 29 5 7 Instruction Set Summary section of the XMEGA A MANUAL for more information 2 5 NVM Commands The NVM commands that can be used for accessing the NVM memories from external programming a...

Страница 6: ...rite Boot Loader Section Page PDI Write 0x39 Boot Loader Section CRC NVMAA Calibration and User Signature sections 0x03 Read User Signature Row PDI Read 0x18 Erase User Signature Row PDI Write 0x1A Wr...

Страница 7: ...hould be removed if PDI programming and debugging is used Other external reset sources driving this line should be disconnected Any load on the clock line may give a delay on the clock edge that cause...

Страница 8: ...is accessed as one linear address space using a dedicated bus PDIBUS between the PDI and the internal interfaces PDI Control and Status Register Space can be accessed with STCS Store and LDCS Load ins...

Страница 9: ...Bus Doing this all data and program memory spaces are mapped into the linear PDI memory space Figure 3 3 shows the PDI memory space and the base address for each memory space in the Atmel ATxmega128A...

Страница 10: ...e data in the Flash or EEPROM page buffer the Flash or EEPROM page must be erased Programming an un erased Flash or EEPROM Page will corrupt the content in the Flash or EEPROM Page 1 Erase Flash or EE...

Страница 11: ...the selected fuse or Lock Bits by doing a PDI Write operation The BUSY flag in the NVM STATUS register will be set until the command is finished For lock bit write the LOCK BIT write command can also...

Страница 12: ...until it has been cleared Erase and program the EEPROM memory 1 Erase the flash page buffer i Use the ST ptr command to set the address 0x00000000 ii Write Erase EEPROM Page Buffer 0x36 command to th...

Страница 13: ...this layer 2 The high level target XMEGA NVM driver which interface the low level PDI driver 3 The low level PDI driver uses the reduced instructions set for the PDI interface to communicate with the...

Страница 14: ...tion can be used here used C xplain_pdi_prog 4 Open either the GCC project file or the IAR project file and compile the source code 5 Connect the USB cable of Atmel Xplain to provide power to the Xpla...

Страница 15: ...AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODU...

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