Atmel AT01080: XMEGA E Schematic Checklist [APPLICATION NOTE]
42087A
−
AVR
−
04/2013
9
5.
TWI Interface
Figure 5-1. TWI interface example schematic.
The TWI module in XMEGA devices follows the electrical specifications and timing of I
2
C bus and SMBus.
The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external components needed
to drive the bus.
Table 5-1. TWI interface checklist.
Signal name
Recommended pin connection
Description
SCL
This pull-up resistor is mandatory on the TWI bus topology since this
line is open-collector line. The value of pull-up resistor Rp will depend
on the SCL frequency:
(fSCL
≤
100kHz, fSCL
≤
400kHz, fSCL
≤
1MHz).
Refer to chapter Two-wire interface characteristics in the datasheet
for choosing the right value.
SCL serial clock line
SDA
This pull-up resistor is mandatory on the TWI bus topology since this
line is open-collector line. The value of pull-up resistor Rp will depend
on the SCL frequency:
(fSCL
≤
100kHz, fSCL
≤
400kHz, fSCL
≤
1MHz).
Refer to chapter Two-wire interface characteristics in the datasheet
for choosing the right value.
SDA serial data line
6.
Suggested Reading
6.1
Datasheets and manual
The datasheet and the manual contain block diagrams of the peripherals and details about implementing firmware for
the device. The datasheet and the manual are available on
section.