364
8331B–AVR–03/12
Atmel AVR XMEGA AU
RESOLUTION is the resolution, 8 or 12 bits. The propagation delay will increase by one extra
ADC clock cycle if the gain stage (GAIN) is used.
The propagation delay is longer than one ADC clock cycle, but the pipelined design means that
the sample rate is limited not by the propagation delay, but by the ADC clock rate.
The most-significant bit (msb) of the result is converted first, and the rest of the bits are con-
verted during the next three (for 8-bit results) or five (for 12-bit results) ADC clock cycles.
Converting one bit takes a half ADC clock period. During the last cycle, the result is prepared
before the interrupt flag is set and the result is available in the result register for readout.
28.9.1
Single Conversion without Gain
shows the ADC timing for a single conversion without gain. The writ-
ing of the start conversion bit, or the event triggering the conversion (START), must occur at
least one peripheral clock cycle before the ADC clock cycle on which the conversion starts (indi-
cated with the grey slope of the START trigger).
The input source is sampled in the first half of the first cycle.
Figure 28-13.
ADC timing for one single conversion without gain.
28.9.2
Single Conversion with Gain
shows the ADC timing for one single conversion with gain. As seen in
the
, the gain stage is placed prior to the actual ADC. The gain stage will
sample and amplify the input source before the ADC samples it, and converts the amplified
value. Compared to a single conversion without gain, this adds one ADC clock cycle (between
START and ADC sample) for the gain stage sample and amplify. The sample time for the gain
stage is one half ADC clock cycle.
CLK
ADC
START
ADC SAMPLE
IF
CONVERTING BIT
10
9
8
7
6
5
4
3
2
1
LSB
1
2
3
4
5
6
7
8
MSB
