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7

AT90S8515

0841GS–09/01

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

Rd, Rr

Add Two Registers

Rd 

 Rd + Rr

Z,C,N,V,H

1

ADC

Rd, Rr

Add with Carry Two Registers

Rd 

 Rd + Rr + C

Z,C,N,V,H

1

ADIW

Rdl, K

Add Immediate to Word

Rdh:Rdl 

 Rdh:Rdl + K

Z,C,N,V,S

2

SUB

Rd, Rr

Subtract Two Registers

Rd 

 Rd - Rr

Z,C,N,V,H

1

SUBI

Rd, K

Subtract Constant from Register

Rd 

 Rd - K

Z,C,N,V,H

1

SBC

Rd, Rr

Subtract with Carry Two Registers

Rd 

 Rd - Rr - C

Z,C,N,V,H

1

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd 

 Rd - K - C

Z,C,N,V,H

1

SBIW

Rdl, K

Subtract Immediate from Word

Rdh:Rdl 

 Rdh:Rdl - K

Z,C,N,V,S

2

AND

Rd, Rr

Logical AND Registers

Rd 

=

Rd 

 Rr

Z,N,V

1

ANDI

Rd, K

Logical AND Register and Constant

Rd 

 Rd 

=

K

Z,N,V

1

OR

Rd, Rr

Logical OR Registers

Rd 

 Rd v Rr

Z,N,V

1

ORI

Rd, K

Logical OR Register and Constant

Rd 

=

Rd v K

Z,N,V

1

EOR

Rd, Rr

Exclusive OR Registers

Rd 

 Rd 

 Rr

Z,N,V

1

COM

Rd

One’s Complement

Rd 

 $FF - Rd

Z,C,N,V

1

NEG

Rd

Two’s Complement

Rd 

 $00 - Rd

Z,C,N,V,H

1

SBR

Rd, K

Set Bit(s) in Register

Rd 

 Rd v K

Z,N,V

1

CBR

Rd, K

Clear Bit(s) in Register

Rd 

 Rd 

 ($FF - K)

Z,N,V

1

INC

Rd

Increment

Rd 

 Rd + 1

Z,N,V

1

DEC

Rd

Decrement

Rd 

 Rd - 1

Z,N,V

1

TST

Rd

Test for Zero or Minus

Rd 

 Rd 

 Rd 

Z,N,V

1

CLR

Rd

Clear Register

Rd 

 Rd 

 Rd

Z,N,V

1

SER

Rd

Set Register

Rd 

 $FF

None

1

BRANCH INSTRUCTIONS

RJMP

k

Relative Jump

PC

=

 PC + k + 1

None

2

IJMP

Indirect Jump to (Z)

PC 

 

Z

None

2

RCALL

k

Relative Subroutine Call

PC 

 PC + k + 1

None

3

ICALL

Indirect Call to (Z)

PC 

 

Z

None

3

RET

Subroutine Return

PC 

 STACK

None

4

RETI

Interrupt Return

PC 

 STACK

I

4

CPSE

Rd, Rr

Compare, Skip if Equal

if (Rd = Rr) PC

=

 PC + 2 or 3

None

1/2/3

CP

Rd, Rr

Compare

Rd - Rr

Z,N,V,C,H

1

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

Z,N,V,C,H

1

CPI

Rd, K

Compare Register with Immediate

Rd - K

Z,N,V,C,H

1

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b) = 0) PC 

 PC + 2 or 3 

None

1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b) = 1) PC 

 PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b) = 0) PC 

 PC + 2 or 3 

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b) = 1) PC 

 PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC 

=

PC + k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC 

=

PC + k + 1

None

1/2

BREQ

k

Branch if Equal

if (Z = 1) then PC 

 PC + k + 1

None

1/2

BRNE

k

Branch if Not Equal

if (Z = 0) then PC 

 PC + k + 1

None

1/2

BRCS

k

Branch if Carry Set

if (C = 1) then PC 

 PC + k + 1

None

1/2

BRCC

k

Branch if Carry Cleared

if (C = 0) then PC 

 PC + k + 1

None

1/2

BRSH

k

Branch if Same or Higher

if (C = 0) then PC 

 PC + k + 1

None

1/2

BRLO

k

Branch if Lower

if (C = 1) then PC 

 PC + k + 1

None

1/2

BRMI

k

Branch if Minus

if (N = 1) then PC 

 PC + k + 1

None

1/2

BRPL

k

Branch if Plus

if (N = 0) then PC 

 PC + k + 1

None

1/2

BRGE

k

Branch if Greater or Equal, Signed

if (N 

 V = 0) then PC 

 PC + k + 1

None

1/2

BRLT

k

Branch if Less Than Zero, Signed

if (N 

 V = 1) then PC 

 PC + k + 1

None

1/2

BRHS

k

Branch if Half-carry Flag Set

if (H = 1) then PC 

 PC + k + 1

None

1/2

BRHC

k

Branch if Half-carry Flag Cleared

if (H = 0) then PC 

 PC + k + 1

None

1/2

BRTS

k

Branch if T-flag Set

if (T = 1) then PC 

 PC + k + 1

None

1/2

BRTC

k

Branch if T-flag Cleared

if (T = 0) then PC 

 PC + k + 1

None

1/2

BRVS

k

Branch if Overflow Flag is Set

if (V = 1) then PC 

 PC + k + 1

None

1/2

BRVC

k

Branch if Overflow Flag is Cleared

if (V = 0) then PC 

 PC + k + 1

None

1/2

BRIE

k

Branch if Interrupt Enabled

if (I = 1) then PC 

 PC + k + 1

None

1/2

BRID

k

Branch if Interrupt Disabled

if (I = 0) then PC 

 PC + k + 1

None

1/2

Содержание AVR AT90S8515

Страница 1: ...d Dual 8 9 or 10 bit PWM On chip Analog Comparator Programmable Watchdog Timer with On chip Oscillator Programmable Serial UART Master Slave SPI Serial Interface Special Microcontroller Features Low power Idle and Power down Modes External and Internal Interrupt Sources Specifications Low power High speed CMOS Process Technology Fully Static Operation Power Consumption at 4 MHz 3V 25 C Active 3 0 ...

Страница 2: ...2 AT90S8515 0841GS 09 01 Pin Configurations ...

Страница 3: ...puts approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed Block Diagram Figure 1 The AT90S8515 Block Diagram The AVR core combines a rich instruction set with 32 general purpose working regis ters All the 32 registers are directly connected to the Arithmetic Logic Unit ALU allowing two independent registers to be accessed in one single instr...

Страница 4: ...ssemblers program debugger simulators in circuit emulators and evaluation kits Pin Descriptions VCC Supply voltage GND Ground Port A PA7 PA0 Port A is an 8 bit bi directional I O port Port pins can provide internal pull up resistors selected for each bit The Port A output buffers can sink 20 mA and can drive LED dis plays directly When pins PA0 to PA7 are used as inputs and are externally pulled l...

Страница 5: ...lses are not guaranteed to generate a reset XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2 Output from the inverting oscillator amplifier ICP ICP is the input pin for the Timer Counter1 Input Capture function OC1B OC1B is the output pin for the Timer Counter1 Output CompareB function ALE ALE is the Address Latch Enable used when the Extern...

Страница 6: ...t Compare Register B High Byte page 39 28 48 OCR1BL Timer Counter1 Output Compare Register B Low Byte page 39 Reserved 25 45 ICR1H Timer Counter1 Input Capture Register High Byte page 39 24 44 ICR1L Timer Counter1 Input Capture Register Low Byte page 39 Reserved 21 41 WDTCR WDTOE WDE WDP2 WDP1 WDP0 page 42 20 40 Reserved 1F 3F EEARH EEAR8 page 44 1E 3E EEARL EEPROM Address Register Low Byte page 4...

Страница 7: ...f Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 PC PC 2 or 3 None 1 2 3 SBRS Rr b Skip if Bit in Register is Set if Rr b 1 PC PC 2 or 3 None 1 2 3 SBIC P b Skip if Bit in I O Register Cleared if P b 0 PC PC 2 or 3 None 1 2...

Страница 8: ...P None 1 OUT P Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I O P b 1 None 2 CBI P b Clear Bit in I O Register I O P b 0 None 2 LSL Rd Logical Shift Left Rd n 1 Rd n Rd 0 0 Z C N V 1 LSR Rd Logical Shift Right Rd n Rd n 1 Rd 7 0 Z C N V 1 ROL Rd Rotate Left through...

Страница 9: ... Commercial 0 C to 70 C AT90S8515 4AI AT90S8515 4JI AT90S8515 4PI 44A 44J 40P6 Industrial 40 C to 85 C 8 4 0V 6 0V AT90S8515 8AC AT90S8515 8JC AT90S8515 8PC 44A 44J 40P6 Commercial 0 C to 70 C AT90S8515 8AI AT90S8515 8JI AT90S8515 8PI 44A 44J 40P6 Industrial 40 C to 85 C Package Type 44A 44 lead Thin 1 0 mm Plastic Gull Wing Quad Flat Package TQFP 44J 44 lead Plastic J leaded Chip Carrier PLCC 40P...

Страница 10: ...75 0 030 0 45 0 018 0 15 0 006 0 05 0 002 0 20 0 008 0 09 0 004 0 7 0 80 0 0315 BSC PIN 1 ID 0 45 0 018 0 30 0 012 PIN 1 Controlling dimension millimetter 44 lead Thin 1 0mm Plastic Quad Flat Package TQFP 10x10mm body 2 0mm footprint 0 8mm pitch Dimension in Millimeters and Inches JEDEC STANDARD MS 026 ACB REV A 04 11 2001 ...

Страница 11: ... 318 0 0125 0 191 0 0075 0 533 0 021 0 330 0 013 0 50 0 020 MIN 3 05 0 120 2 29 0 090 4 57 0 180 4 19 0 165 16 70 0 656 16 50 0 650 17 70 0 695 17 40 0 685 SQ SQ 2 11 0 083 1 57 0 062 16 00 0 630 15 00 0 590 SQ 44J 44 lead Plastic J leaded Chip Carrier PLCC Dimensions in Milimeters and Inches JEDEC STANDARD MS 018 AC Controlling dimensions Inches REV A 04 11 2001 ...

Страница 12: ... 88 0 625 15 24 0 600 1 65 0 065 1 27 0 050 17 78 0 700 MAX 0 38 0 015 0 20 0 008 2 54 0 100 BSC 3 56 0 140 3 05 0 120 SEATING PLANE 4 83 0 190 MAX 48 26 1 900 REF 0º 15º 40 lead Plastic Dual Inline Parkage PDIP 0 600 wide Demension in Millimeters and Inches JEDEC STANDARD MS 011 AC Controlling dimension Inches REV A 04 11 2001 ...

Страница 13: ...41 26 426 5555 FAX 41 26 426 5500 Asia Atmel Asia Ltd Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721 9778 FAX 852 2722 1369 Japan Atmel Japan K K 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 7581 Atmel Colorado Springs 1150 E Cheyenne Mtn Blvd Colorado Springs CO 80906 TEL 719 576 3300 FAX 719 5...

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