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AT90S8515
0841GS–09/01
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not active.
Port D also serves the functions of various special features of the AT90S8515 as listed
on page 73.
RESET
Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the
clock is not running. Shorter pulses are not guaranteed to generate a reset.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
ICP
ICP is the input pin for the Timer/Counter1 Input Capture function.
OC1B
OC1B is the output pin for the Timer/Counter1 Output CompareB function.
ALE
ALE is the Address Latch Enable used when the External Memory is enabled. The ALE
strobe is used to latch the low-order address (8 bits) into an address latch during the first
access cycle, and the AD0 - 7 pins are used for data during the second access cycle.
