Atmel AT91SAM9263-EK, Руководство пользователя

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AT91SAM9263-EK Evaluation Board User Guide 3-1
6325D–ATARM–26-Aug-09
Section 3
Board Description
3.1 AT91SAM9263 Microcontroller
„ Incorporates the ARM926EJ-S
™
ARM
®
Thumb
®
Processor
– DSP Instruction Extensions, Jazelle
®
Technology for Java
®
Acceleration
– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
– 200 MIPS at 180 MHz
– Memory Management Unit
– EmbeddedICE
™
, Debug Communication Channel Support
– Mid-level Implementation Embedded Trace Macrocell
™
„ Bus Matrix
– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth
– Boot Mode Select Option, Remap Command
„ Embedded Memories
– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed
– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor Bus Matrix Speed
– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed
„ Dual External Bus Interface (EBI0 and EBI1)
– EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
®
– EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash
„ DMA Controller (DMAC)
– Acts as one Bus Matrix Master
– Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel
Buffering and Control
„ Twenty Peripheral DMA Controller Channels (PDC)
„ LCD Controller
– Supports Passive or Active Displays
– Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers
„ 2D Graphics Accelerator
– Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing
„ Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format