30
AT90S/LS2323/2343
1004D–09/01
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK oscillator clock. If the external pin modes are
used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is
configured as an output. This feature can give the user software control of the counting.
Timer/Counter0 – TCNT0
The Timer/Counter0 is realized as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues
counting in the timer clock cycle following the write operation.
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 11. See characterization data for typical values at other V
CC
levels. The WDR
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the AT90S2323/2343 resets and executes from the reset vec-
tor. For timing details on the Watchdog reset, refer to page 23.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 31.
Watchdog Timer
Bit
7
6
5
4
3
2
1
0
$32 ($52)
MSB
LSB
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
1 MHz at V
CC
= 5V
350 kHz at V
CC
= 3V
Oscillator
