46
English
tWRWR_dg
Conigure between module write to write delay.
tWRWR_dr
Conigure between module write to write delay.
tWRWR_dd
Conigure between module write to write delay.
RTL (CH A)
Conigure round trip latency for channel A.
RTL (CH B)
Conigure round trip latency for channel B.
IO-L (CH A)
Conigure IO latency for channel A.
IO-L (CH B)
Conigure IO latency for channel B.
Fourth Timing
twRPRE
Conigure twRPRE.
Write_Early_ODT
Conigure Write_Early_ODT.
tAONPD
Conigure tAONPD.
tXP
Conigure tXP.
tXPDLL
Conigure tXPDLL.
tPRPDEN
Содержание H170M-ITX/DL
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