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English
H170M-ITX/DL
DRAM Timing Coniguration
Load XMP Setting
Load XMP settings to overclock the memory and perform beyond standard speciications.
BCLK Frequency
he CPU speed is determined by the CPU Ratio multiplied with the BCLK.
Increasing the BCLK will increase the internal CPU clock speed but also afect the
clock speed of other components.
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
Primary Timing
CAS# Latency (tCL)
he time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay and Row Precharge (tRCDtRP) O
RAS# to CAS# Delay : he number of clock cycles required between the opening of
a row of memory and accessing columns within it.
Row Precharge: he number of clock cycles required between the issuing of the
precharge command and opening the next row.
RAS# Active Time (tRAS)
he number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
he delay between when a memory chip is selected and when the irst active command can
be issued.
Secondary Timing
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