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ASIC Bitmain Antminer S9K, Руководство по обслуживанию

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                                                                                      S9k S9SE Maintenance Guide 

 

2 

 

2. Analysis of key point  

2.1 The following figure shows the chip domain distribution, signal path and circuit distribution of the S9K S9SE signal board: 

 
 

 

 

DC

输入口

 

DC input 
IO

座

J4 

IO Block J4 

钳位电路

 

Clamping circuit 
EEPROM

芯片

 

EEPROM chip 

域电压信号电平转换

IC 

Domain voltage signal level shifting IC 
TMP 451

温感

 

TMP 451 temperature sense 
 

DC-DC 

IO

座

J4 

钳位电路

 

DC

输入口

 

域电压信号

电平转换

IC 

EEPROM

芯片

 

域

1 

域

6 

域

5 

域

3 

域

4 

域

1 

域

2 

TMP45

1

温感

  

TMP45

1

温感

  

Содержание Bitmain Antminer S9K

Страница 1: ...es of the single board test jig program III Principle and Structure 1 Principle overview 1 S9K S9SE computing board is composed of 6 voltage domains connected in series There are 10 BM1393 chips in ea...

Страница 2: ...chip domain distribution signal path and circuit distribution of the S9K S9SE signal board DC DC input IO J4 IO Block J4 Clamping circuit EEPROM EEPROM chip IC Domain voltage signal level shifting IC...

Страница 3: ...from chip U60 to chip U1 and then returns to the control board from the pin J4 8 at IO port when the IO signal is not inserted the voltage is 1 8V and the voltage is 1 8V when computing Signal BO BI...

Страница 4: ...2 Schematic diagram of DC to DC circuit 2 2 3 Schematic diagram of EEPROM IC single board test will change the magic number temperature sensing information and CRC information in the EEPROM 2 2 4 Sche...

Страница 5: ...S9k S9SE Maintenance Guide 5 2 2 5 Schematic diagram of PIC U102 2 2 6 Signal test points of each chip as shown below after amplified...

Страница 6: ...S9k S9SE Maintenance Guide 6 1 3 5 Signal test points in Domain 1 3 5 2 4 6 Signal test points in Domain 2 4 6 2 2 7 Pin circuit diagram of each chip in Domain 1 3 and 5 1 3 5 2 4 6...

Страница 7: ...S9k S9SE Maintenance Guide 7 2 2 8 Pin circuit diagram of each chip in Domain 2 4 and 6 2 2 9 Circuit diagram of J4 at IO port...

Страница 8: ...S9k S9SE Maintenance Guide 8 2 2 10 0 8V 1 8V circuit schematic diagram 2 2 11 Schematic diagram for Level signal conversion...

Страница 9: ...S9k S9SE Maintenance Guide 9 2 2 12 Schematic diagram for Y1 Y2 crystal oscillator 2 2 13 LDO 0 8V 1 8V and crystal oscillator measurement...

Страница 10: ...tage set by the test program of PIC jig and boosts as it works Then the jig outputs WORK and returns to noce after computing At this point the normal voltage of each test point should be CLKO 0 9V CO...

Страница 11: ...nd several of the signals CLK CO BO NRST are transmitted forward U1 U60 and an abnormal fault point is found through the power supply sequence 5 When locating to the faulty chip the chip needs to be r...

Страница 12: ...mple a chip itself can work but it will not forward other chip information at this time the entire signal chain will come to an abrupt end and lose a large part of it which is called broken chain The...

Страница 13: ...nt signal apart from the metal exposed at the contact end the other parts of the test lead must be sealed with a heat shrinkable tube so as to prevent the test lead from contacting with the cooling fi...

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