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                                                                                      S9k S9SE Maintenance Guide 

 

 

  

Instructions for S9K S9SE Maintenance 

Editor-in-Chief: 

Wang Penghua

 

Version date: 

2019.7.9

 

File Category: 

Maintenance Plan

 

Content of this Volume: 

It mainly describes the troubleshooting of various faults of S9K S9SE, and how to use the test tool for accurate positioning. 

 

 

 

I. Requirements on the Maintenance Platform  

1. The constant temperature soldering iron (350-400°C). The tip soldering iron head is used for soldering chip resistors and capacitors.  
2. The thermal chimney is used for chip disassembly and soldering, be careful not to heat for a long time to avoid PCB foaming. 
3. APW3 + + power supply (output 

12V, 133A Max

), used for test and measurement of the computing board. 

4. The multimeter, tweezers, 

V9 

test jig (if there is condition, an oscilloscope can be configured). 

5. Flux, water for cleaning panel with anhydrous alcohol; water for cleaning panel is used to clean flux residue and appearance after maintenance. 
7. Thermally conductive adhesive is used to re-attach the cooling fin after repair. 

 

II. Requirements on Maintenance Operations 

1. The maintenance personnel must have certain electronic knowledge, more than one year of maintenance experience, and master QFN package welding 

technology. 

2. After repair, the computing board must be tested twice and confirmed as OK before it can pass! 

3. Pay attention to the operation method when replacing the chip. After replacing any accessories, the PCB board is not obviously deformed, and the replaced 

parts and the surrounding area shall be checked for whether there is open and short circuit. 

4. Determine the maintenance station object and the corresponding test software parameters and test jigs. 

5. Check whether the tools and jigs can work normally. 

(Whether the power output is the same as the setting in the jig config file. Different BIN level and chip package mode need to correspond to the config and 

single-board-test files of the single board test jig program.) 

 

 

 

III. Principle and Structure 

1. Principle overview 

   

1. S9K S9SE computing board 

is composed of 6 voltage domains connected in series. There are

 10 BM1393 

chips in each voltage domain, and there are

 60 

BM1393 

chips on the whole board.

 

2. 

There are 208 cores on a single 

BM1393 

chip, the domain voltage is 1.6V, and the total voltage of the 6 domains on the whole board is 9.6V-9.9V 

3. S9K S9SE clock is composed of two 25M active crystal oscillators (Y1, Y2), Y1 is transmitted from the first chip to the 30th chip in series, and Y2 

is transmitted from the 31st chip to the 60th chip in series 

4.

 There is independent small cooling fin on the front and back of each chip of the 

S9K S9SE computing board. 

The small cooling fin on the front side is the 

SMT patch, and the small cooling fin on the back side is fixed on the back of the IC by the thermally conductive adhesive after the initial measurement. After 

the repaired and replaced chip passes the test, it is necessary to evenly apply black thermally conductive adhesive on the IC surface and heat and fix it.

 

 

 

 

 

Note: 

   

In the maintenance process, when replacing the circuit board components or the chip, in order to reduce the damage of high temperature of the blower gun to 

the PCB board and the chip, it is necessary to first remove the small cooling fins near the faulty component and on the back of the PCB board before 

replacing. 

 
There are test points on the PCB chip surfaces. When manufacturing and repairing, if there is no cooling fin attached on the PCB chip, the test point on the 

chip surface can be used; for repair of finished products (after-sales repair), since the front and back of the PCB are covered by cooling fins, it needs to locate 

fault through the test point on the chip surface of the PCB. A special slender test lead can be used to probe the cooling fin gap for measurement. However, 

since the SMT small cooling fin is connected to the ground of each voltage domain, it is necessary to pay attention to the insulation of the test lead in 

measurement to avoid short circuit caused by the test lead. 

 
  
 
 
 
 
 
 

 

Содержание Bitmain Antminer S9K

Страница 1: ...es of the single board test jig program III Principle and Structure 1 Principle overview 1 S9K S9SE computing board is composed of 6 voltage domains connected in series There are 10 BM1393 chips in ea...

Страница 2: ...chip domain distribution signal path and circuit distribution of the S9K S9SE signal board DC DC input IO J4 IO Block J4 Clamping circuit EEPROM EEPROM chip IC Domain voltage signal level shifting IC...

Страница 3: ...from chip U60 to chip U1 and then returns to the control board from the pin J4 8 at IO port when the IO signal is not inserted the voltage is 1 8V and the voltage is 1 8V when computing Signal BO BI...

Страница 4: ...2 Schematic diagram of DC to DC circuit 2 2 3 Schematic diagram of EEPROM IC single board test will change the magic number temperature sensing information and CRC information in the EEPROM 2 2 4 Sche...

Страница 5: ...S9k S9SE Maintenance Guide 5 2 2 5 Schematic diagram of PIC U102 2 2 6 Signal test points of each chip as shown below after amplified...

Страница 6: ...S9k S9SE Maintenance Guide 6 1 3 5 Signal test points in Domain 1 3 5 2 4 6 Signal test points in Domain 2 4 6 2 2 7 Pin circuit diagram of each chip in Domain 1 3 and 5 1 3 5 2 4 6...

Страница 7: ...S9k S9SE Maintenance Guide 7 2 2 8 Pin circuit diagram of each chip in Domain 2 4 and 6 2 2 9 Circuit diagram of J4 at IO port...

Страница 8: ...S9k S9SE Maintenance Guide 8 2 2 10 0 8V 1 8V circuit schematic diagram 2 2 11 Schematic diagram for Level signal conversion...

Страница 9: ...S9k S9SE Maintenance Guide 9 2 2 12 Schematic diagram for Y1 Y2 crystal oscillator 2 2 13 LDO 0 8V 1 8V and crystal oscillator measurement...

Страница 10: ...tage set by the test program of PIC jig and boosts as it works Then the jig outputs WORK and returns to noce after computing At this point the normal voltage of each test point should be CLKO 0 9V CO...

Страница 11: ...nd several of the signals CLK CO BO NRST are transmitted forward U1 U60 and an abnormal fault point is found through the power supply sequence 5 When locating to the faulty chip the chip needs to be r...

Страница 12: ...mple a chip itself can work but it will not forward other chip information at this time the entire signal chain will come to an abrupt end and lose a large part of it which is called broken chain The...

Страница 13: ...nt signal apart from the metal exposed at the contact end the other parts of the test lead must be sealed with a heat shrinkable tube so as to prevent the test lead from contacting with the cooling fi...

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