Asahi KASEI AK4588 Скачать руководство пользователя страница 14

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ASAHI KASEI

[AK4589]

MS0339-E-00

2004/09

SWITCHING CHARACTERISTICS (ADC/DAC part)

(Ta=25

C; AVDD, DVDD, PVDD=4.75

∼

5.25V; TVDD=2.7

∼

5.25V; C

=20pF)

Parameter Symbol

min

typ

max

Units

Master Clock Timing

Master Clock

256fsn, 128fsd:

Pulse Width Low
Pulse Width High

384fsn, 192fsd:

Pulse Width Low
Pulse Width High

512fsn, 256fsd, 128fsq:

Pulse Width Low
Pulse Width High

fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH

8.192

27
27

12.288

20
20

16.384

15
15

12.288

18.432

24.576

MHz

ns
ns

MHz

ns
ns

MHz

ns
ns

LRCK1 Timing (Slave Mode)

Normal mode

Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle

fsn
fsd
fsq
Duty

32
64

120

48
96

192

kHz
kHz
kHz

TDM 256 mode

LRCK1 frequency
“H” time
“L” time

fsd
tLRH
tLRL

1/256fs
1/256fs

kHz

ns
ns

TDM 128 mode

LRCK1 frequency
“H” time
“L” time

fsd
tLRH
tLRL

1/128fs
1/128fs

kHz

ns
ns

LRCK1 Timing (Master Mode)

Normal mode

Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle

fsn
fsd
fsq
Duty

32
64

120

48
96

192

kHz
kHz
kHz

TDM 256 mode

LRCK1 frequency
“H” time (Note 16)

fsn
tLRH

1/8fs

kHz

TDM 128 mode

LRCK1 frequency
“H” time (Note 16)

fsd
tLRH

1/4fs

kHz

Power-down & Reset Timing

PDN Pulse Width (Note 17)

PDN “

↑

” to SDTO1 valid (Note 18)

tPD
tPDV

150

522

1/fs

Notes:

16. “L” time at I

S format.

17. The AK4589 can be reset by bringing PDN “L” to “H” upon power-up.
18. These cycles are the number of LRCK rising from PDN rising.

Содержание AK4588

Страница 1: ...The DIR has 8 channel input selector and can automatically detect a Non PCM bit stream The AK4589 provides a compatibility of hardware and software with the AK4588 Dolby Digital AC 3 is a trademark o...

Страница 2: ...ing Frequency Detection 32kHz 44 1kHz 48kHz 88 2kHz 96kHz 176 4kHz 192kHz Unlock Parity Error Detection Validity Flag Detection Up to 24bit Audio Data Format Audio I F Master or Slave Mode 40 bit Chan...

Страница 3: ...3 RX4 RX5 RX6 RX7 DIT TX0 Error Detect STATUS INT1 Q subcode buffer TX1 B C U VOUT 8 to 3 VIN Audio I F SCF SCF SCF SCF SCF SCF LOUT1 ROUT1 LOUT2 ROUT2 LOUT3 ROUT3 DAC DATT DEM ADC HPF ADC HPF RIN LIN...

Страница 4: ...31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20...

Страница 5: ...3 0Vpp Typ 2 7Vpp DAC AOUT AOUT 0 6xVREFH AOUT 0 54xVREFH Load Resistance 5k ohm 2k ohm Frequency Response 80kHz 1 0 0 0 6 Output pin 35 37 39 41 43 45 47 49 35 50 Power Supply voltage Min 4 5V Max 5...

Страница 6: ...io Serial Data Clock Pin DIR DIT part 16 LRCK2 I O Channel Clock Pin DIR DIT part 17 SDTO1 O Audio Serial Data Output Pin ADC DAC part 18 BICK1 I O Audio Serial Data Clock Pin ADC DAC part 19 LRCK1 I...

Страница 7: ...4 O DAC4 Rch Negative Analog Output Pin 38 ROUT4 O DAC4 Rch Positive Analog Output Pin 470pF capacitor should be connected between ROUT4 and ROUT4 39 LOUT3 O DAC3 Lch Negative Analog Output Pin 40 LOU...

Страница 8: ...5 25V 67 RX4 I Receiver Channel 4 Pin Internal biased pin Internally biased at PVDD 2 68 TEST2 I Test 2 Pin This pin should be connected to PVSS 69 RX5 I Receiver Channel 5 Pin Internal biased pin Int...

Страница 9: ...as below Classification Pin Name Setting Analog RX0 7 LOUT1 4 ROUT1 4 LIN RIN These pins should be open INT0 1 BOUT XTO MCKO1 2 COUT UOUT VOUT SDTO1 2 CDTO DZF1 2 TX1 0 These pins should be open CSN...

Страница 10: ...age Temperature Tstg 65 150 C Notes 1 All voltages with respect to ground 2 AVSS DVSS and PVSS must be connected to the same analog ground plane WARNING Operation at or beyond these limits may result...

Страница 11: ...Vpp Input Resistance fs 48kHz fs 96kHz 15 9 25 16 k k Power Supply Rejection Note 7 50 dB DAC Analog Output Characteristics Resolution 24 Bits S N D fs 48kHz fs 96kHz fs 192kHz 86 84 94 92 92 dB dB dB...

Страница 12: ...tion SA 68 dB Group Delay Note 13 GD 16 1 fs Group Delay Distortion GD 0 s ADC Digital Filter HPF Frequency Response Note 12 3dB 0 1dB FR 1 0 6 5 Hz Hz DAC Digital Filter Passband Note 12 0 1dB 6 0dB...

Страница 13: ...cept TX0 1 DZF pins Iout 400 A TX0 1 pin Iout 400 A DZF pin Iout 400 A Low Level Output Voltage Iout 400 A VOH VOH VOH VOL TVDD 0 4 DVDD 0 4 AVDD 0 4 0 4 V V V V Input Leakage Current Iin 10 A Note 15...

Страница 14: ...cle fsn fsd fsq Duty 32 64 120 45 48 96 192 55 kHz kHz kHz TDM 256 mode LRCK1 frequency H time L time fsd tLRH tLRL 32 1 256fs 1 256fs 48 kHz ns ns TDM 128 mode LRCK1 frequency H time L time fsd tLRH...

Страница 15: ...e 19 BICK1 to SDTO1 SDTI1 2 Hold Time SDTI1 2 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns Audio Interface Timing Master Mode Normal mode BICK1...

Страница 16: ...DAC part 1 fCLK tCLKL VIH tCLKH MCLK VIL 1 fsn 1 fsd 1 fsq LRCK1 VIH VIL tBCK tBCKL VIH tBCKH BICK1 VIL Clock Timing Normal mode 1 fCLK tCLKL VIH tCLKH MCLK VIL 1 fs LRCK1 VIH VIL tLRL tLRH tBCK tBCK...

Страница 17: ...B LRCK1 VIH BICK1 VIL tLRS SDTO1 50 TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Audio Interface Timing Normal mode tLRB LRCK1 VIH BICK1 VIL SDTO1 50 TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Aud...

Страница 18: ...ASAHI KASEI AK4589 MS0339 E 00 2004 09 18 LRCK1 BICK1 SDTO1 tBSD tMBLR 50 TVDD 50 TVDD 50 TVDD DAUX1 tDXH tDXS VIH VIL Audio Interface timing Master Mode...

Страница 19: ...Clock Recover Frequency RX0 7 fpll 32 192 kHz LRCK2 Frequency Duty Cycle fs dLCK 32 45 192 55 kHz Audio Interface Timing Slave Mode BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BI...

Страница 20: ...TVDD MCKO1 tMCKL1 tMCKH1 dMCK1 tMCKH1 x fMCK1 x 100 tMCKL1 x fMCK1 x 100 1 fMCK2 50 TVDD MCKO2 tMCKL2 tMCKH2 dMCK2 tMCKH2 x fMCK2 x 100 tMCKL2 x fMCK2 x 100 1 fs LRCK2 VIH VIL tLRL tLRH dLCK tLRH x f...

Страница 21: ...ASAHI KASEI AK4589 MS0339 E 00 2004 09 21 LRCK2 BICK2 SDTO2 tBSD tMBLR 50 TVDD 50 TVDD 50 TVDD DAUX2 tDXH tDXS VIH VIL Serial Interface Timing Master Mode tPW PDN VIL Power Down Reset Timing...

Страница 22: ...Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling Note 23 SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SC...

Страница 23: ...TE READ Command Input Timing in 4 wire serial mode The ADC DAC part doesn t support READ command tCSW CSN CCLK CDTI D2 D0 tCSH CDTO Hi Z D1 D3 VIH VIL VIH VIL VIH VIL WRITE Data Input Timing in 4 wire...

Страница 24: ...Data Input Timing 2 in 4 wire serial mode The ADC DAC part doesn t support READ command tHIGH SCL SDA VIH tLOW tBUF tHD STA tR tF tHD DAT tSU DAT tSU STA Stop Start Start Stop tSU STO VIL VIH VIL tSP...

Страница 25: ...use the device utilizes dynamic refreshed logic internally If the external clocks are not present the AK4589 should be in the power down mode PDN pin L or in the reset mode RSTN1 bit 0 After exiting r...

Страница 26: ...uto Setting Mode De emphasis Filter The AK4589 includes the digital de emphasis filter tc 50 15 s by IIR filter De emphasis filter is not available in Double Speed Mode and Quad Speed Mode This filter...

Страница 27: ...M J 24bit L J H L I 48fs I 2 0 0 0 1 0 24bit M J 24bit M J H L I 48fs I 3 0 0 0 1 1 24bit I2 S 24bit I2 S L H I 48fs I 4 1 0 0 0 0 24bit M J 20bit L J H L O 64fs O 5 1 0 0 0 1 24bit M J 24bit L J H L...

Страница 28: ...t I2 S 24bit I2 S O 256fs O Table 11 Audio data formats TDM 256 mode M J shows MSB justified L J means LSB justified LRCK1 BICK1 Mode MASTER TDM 1 TDM0 DIF1 DIF0 SDTO1 SDTI1 SDTI2 I O I O 16 0 1 1 0 0...

Страница 29: ...15 14 0 23 SDTI i 1 22 0 23 8 7 1 22 0 23 8 7 23 MSB 0 LSB Lch Data Rch Data Don t Care Don t Care 16 15 14 Figure 2 Mode 1 5 Timing LRCK1 BICK1 64fs SDTO1 o 0 1 2 21 22 23 24 31 0 1 2 0 23 1 22 1 23...

Страница 30: ...32 BICK 22 0 R4 32 BICK 22 0 Rch 32 BICK 22 23 23 23 23 23 23 23 23 23 23 23 23 LRCK1 LRCK1 mode 9 mode 13 Figure 6 Mode 9 13 Timing 256 BICK BICK1 256fs SDTO1 o SDTI1 i 22 0 Lch 32 BICK 22 0 L1 32 B...

Страница 31: ...0 Lch 32 BICK L1 32 BICK R1 32 BICK L2 32 BICK R2 32 BICK L3 32 BICK R3 32 BICK L4 32 BICK R4 32 BICK 22 0 Rch 32 BICK 22 23 23 23 SDTI1 i 22 0 22 0 22 0 22 0 23 23 23 23 19 LRCK1 SDTI2 i 22 0 22 0 2...

Страница 32: ...2 0 Lch 32 BICK L1 32 BICK R1 32 BICK L2 32 BICK R2 32 BICK L3 32 BICK R3 32 BICK L4 32 BICK R4 32 BICK 22 0 Rch 32 BICK 23 23 23 SDTI1 i 22 0 22 0 22 0 22 0 23 23 23 23 23 SDTI2 i 22 0 22 0 22 0 22 0...

Страница 33: ...E bit and DZF When the input data of all channels in the group 1 group 2 are continuously zeros for 8192 LRCK1 cycles DZF1 DZF2 pin goes to H DZF1 DZF2 pin immediately goes to L if input data of any c...

Страница 34: ...TT7 0 bits can be selected by ATS1 0 bits Table 16 Transition between set values is the soft transition Therefore the switching noise does not occur in the transition Mode ATS1 ATS0 ATT speed 0 0 0 17...

Страница 35: ...ransition time Table 16 For example in Normal Speed Mode this time is 1792LRCK1 cycles 1792 fs at ATT_DATA 00H ATT transition of the soft mute is from 00H to 7FH 2 The analog output corresponding to t...

Страница 36: ...e analog output should muted externally if the click noise influences system application ADC Internal State PDN pin Clock In MCLK LRCK1 BICK1 ADC In Analog ADC Out Digital DAC Internal State DAC In Di...

Страница 37: ...The analog part of ADC is initialized after exiting the reset state 2 Digital output corresponding to analog input and analog output corresponding to digital input have the group delay GD 3 ADC output...

Страница 38: ...Analog GD GD 1 3 3 2 DAC Digital Internal State Normal Operation Normal Operation DAC Analog Internal State Power down Normal Operation Clock In MCLK LRCK1 BICK1 DAC In Digital DAC Out Analog Normal O...

Страница 39: ...PD2 PD1 RSTN1 0AH Zero detect OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN 0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 AT...

Страница 40: ...et to 0 at TDM bit 1 In the case of PWADN bit 0 and PWDAN bit 0 the setting of SDOS bit becomes invalid And ADC is selected The output of SDTO1 becomes L at PWADN bit 0 LOOP1 0 Loopback mode enable 00...

Страница 41: ...BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Default 0 0 0 0 0 0 0 0 ATT7 0 Attenuation Level see Table 15 Addr Regi...

Страница 42: ...ower down control of DAC1 PD2 Power down control of DAC2 PD3 Power down control of DAC3 PD4 Power down control of DAC4 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Zero detect OVFE DZFM3 DZFM2 DZFM1...

Страница 43: ...z 88 2kHz 96kHz 176 4kHz and 192kHz The PLL loses lock when the received sync interval is incorrect Master Clock The AK4589 has two clock outputs MCKO1 and MCKO2 These clocks are derived from either t...

Страница 44: ...mode Note External capacitance depends on the crystal oscillator Typ 10 40pF 2 External clock Note Input clock must not exceed DVDD XTI XTO AK4589 25k External Clock typ XTI XTO AK4589 25k External C...

Страница 45: ...1 Others 0 0 1 0 48kHz 48kHz 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32kHz 32kHz 0 0 1 1 1 1 0 0 0 0 1 0 0 0 88 2kHz 88 2kHz 1 0 0 0 0 0 1 0 1 0 1 0 1 0 96kHz 96kHz 1 0 1 0 0 0 0 0 1 0 1 1 0 0 176 4kHz 176 4kHz 1...

Страница 46: ...1 0 0 1 OFF Default 1 0 1 0 48kHz 1 0 1 1 32kHz 1 1 0 0 OFF 1 1 0 1 OFF 1 1 1 0 96kHz 1 1 1 1 OFF 0 x x x OFF Table 24 De emphasis Manual Control at DEAU bit 0 System Reset and Power Down The AK4589 h...

Страница 47: ...or more IPS2 0 bits selects the receiver channel When BCU bit 1 the Block start signal C bit and U bit can output from each pins IPS2 IPS1 IPS0 INPUT Data 0 0 0 RX0 Default 0 0 1 RX1 0 1 0 RX2 0 1 1 R...

Страница 48: ...or left channel and output 0100 at C20 23 for right channel automatically When CT20 bit is 0 AK4589 outputs 0000 set as 1000 for sub frame 1 and 0100 for sub frame 2 U bits are fixed to 0 as C20 23 fo...

Страница 49: ...Receiver Optical Fiber Figure 24 Consumer Input Circuit Optical Input In case of coaxial input as the input level of RX line is small in Serial Mode be careful not to crosstalk among RX input lines F...

Страница 50: ...er of 0 min 0 max 8 Figure 26 Configuration of U bit CD Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 CTRL ADRS TRACK NUMBER INDEX Q26 Q27 Q28 Q29 Q30 Q31 Q32...

Страница 51: ...e changed by EFH0 1 bits after those events are removed INT1 pin goes to L at the same time when those events are removed Each INT0 1 pins can mask those eight events individually Once PAR QINT and CI...

Страница 52: ...K Previous Data Register PAR CINT QINT Hold 1 Command READ 06H MCKO BICK2 LRCK2 except UNLOCK fs around 20kHz SDTO2 PAR error Hold Time 0 Reset Error SDTO2 others Normal Operation INT0 pin Hold Time m...

Страница 53: ...39 E 00 2004 09 53 INT0 1 pin H No Yes Yes Initialize PDN pin L to H Read 06H Mute DAC output Read 06H No Each Error Handling Read 06H Resets registers INT0 1 pin H Release Muting Figure 30 Error Hand...

Страница 54: ...2004 09 54 INT1 pin H No Yes Initialize PDN pin L to H Read 06H Read 06H and Detect QSUB 1 No Read Q buffer New data is valid INT1 pin L QCRC 0 Yes Yes New data is invalid No Figure 31 Error Handling...

Страница 55: ...the data is transformed and output from SDTO2 DAUX2 pin is used in Clock Operation Mode 1 3 and unlock state of Mode 2 The input data format to DAUX2 should be left justified except in Mode5 and 7 Ta...

Страница 56: ...0 1 12 21 20 20 21 12 22 23 22 23 Figure 34 Mode 3 Timing LRCK2 BICK2 64fs SDTO2 0 1 2 31 0 1 23 MSB 0 LSB Lch Data Rch Data 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 3 2 23 22 Figure...

Страница 57: ...el Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 CT29 CT28 CT27 CT26 CT25 CT24 11H TX Channel Status Byte 4 CT39 CT39 CT39 CT39 CT39 CT39 CT39 CT32 12H B...

Страница 58: ...COUT UOUT become to be enabled The block signal goes high at the start of frame 0 and remains high until the end of frame 31 CS12 Channel Status Select 0 Channel 1 1 Channel 2 Selects which channel s...

Страница 59: ...outputs L 1 Enable TX1E TX1 Output Enable 0 Disable TX1 pin outputs L 1 Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Input Output Control 1 EFH1 EFH0 UDIT 0 DIT IPS2 IPS1 IPS0 R W R W R W R W...

Страница 60: ...t MCI0 Mask Enable for CINT bit MAT0 Mask Enable for AUTO bit MQI0 Mask Enable for QINT bit 0 Mask disable 1 Mask enable Mask Control for INT1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H INT1 MASK...

Страница 61: ...nel status bits DTSCD DTS CD Auto Detect 0 No detect 1 Detect UNLCK PLL Lock Status 0 Locked 1 Out of Lock CINT Channel Status Buffer Interrupt 0 No change 1 Changed AUTO Non PCM Auto Detect 0 No dete...

Страница 62: ...CT5 CT4 CT3 CT2 CT1 CT0 0EH TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 0FH TX Channel Status Byte 2 CT23 CT22 CT21 CT20 CT19 CT18 CT17 CT16 10H TX Channel Status Byte 3 CT31 CT30 C...

Страница 63: ...Q23 Q22 Q21 Q20 Q19 Q18 19H Q subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 1AH Q subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 1BH Q subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 1CH Q subcode Zer...

Страница 64: ...MSB V U C P sub frame of IEC958 0 15 Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 37 Data structure in IEC60958 Preamble word Length of field Contents Value Pa 16 bits sync...

Страница 65: ...2 data with extension MPEG 2 AAC ADTS MPEG 2 Layer1 Low sample rate MPEG 2 Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2 3 reserved 4096 1536 384 1152 1152 1024...

Страница 66: ...c2 0 Pd1 Pd2 Pd3 Pc3 PDN pin Bit stream AUTO bit Pc Register Pd Register Repetition time 4096 frames Figure 38 Timing example 1 2 When Non PCM bitstream stops when MULK0 0 Pa Pc1 Pd1 Pb Stop Pa Pcn Pd...

Страница 67: ...ut on the falling edge For write operations data is latched after the 16th rising edge of CCLK after a high to low transition of CSN For read operations the CDTO output goes high impedance after a low...

Страница 68: ...ACKNOWLEDGE The data transfer is always terminated by a STOP condition generated by the master device 2 1 1 Data validity The data on the SDA line must be stable during the HIGH period of the clock Th...

Страница 69: ...ons SCL FROM MASTER acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 1 9 8 START CONDITION Clock pulse for acknowledge not acknowledge Figure 43 Acknowledge on the I2 C bus 2 1 4 FIRST B...

Страница 70: ...irst 8bits D7 D6 D5 D4 D3 D2 D1 D0 Figure 46 Byte structure after the second byte The AK4589 is capable of more than one byte write operation by one sequence After receipt of the third byte the AK4589...

Страница 71: ...AK4589 generates an acknowledge transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1 If the master does not generate an acknowled...

Страница 72: ...l 0 1u 10u C1 C1 12 13 14 15 16 69 68 67 66 65 32 33 34 35 36 49 48 47 46 45 SDTO2 UOUT MCKO2 COUT XTO XTI SCL CSN SDTI4 MASTER LOUT4 LOUT1 ROUT1 ROUT1 RX0 RX1 TEST2 CAD0 RX5 RX6 INT0 MUTE SDTO1 LRCK1...

Страница 73: ...locks should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4589 3 Analog Inputs ADC inputs are single ended and internally biased to VCOM The input signal ra...

Страница 74: ...LPF NJM5534D are op amps that has low noise and 15V power supply operation 330 100u 180 AOUTL 10k 3 9n 1 2k 680 3 3n 6 4 3 2 7 10u 0 1u 0 1u 10u 10u NJM5534D 330 100u 180 AOUTL 10k 3 9n 1 2k 680 3 3n...

Страница 75: ...LQFP Unit mm 14 0 0 2 12 0 0 2 0 50 1 20 21 40 41 60 61 80 12 0 0 2 14 0 0 2 1 25TYP 0 08 M 0 125 0 10 0 05 0 50 0 1 1 85MAX 0 10 0 15 0 10 1 40 0 2 0 10 0 20 0 1 0 10 Material Lead finish Package Epo...

Страница 76: ...related device or system and AKM assumes no responsibility relating to any such use except with the express written consent of the Representative Director of AKM As used here a A hazard related device...

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