500-003111-000
3-2
3.3.1 Read/Write
Operations
During each READ/WRITE operation, all VMEbus control signals are
ignored unless the board selection comparator detects a match between the
on-board selection jumpers shown in Figure 3.3.1-1 and the address and address
modifier lines from the backplane. The appropriate board response occurs if a
valid match is detected, after which the open-collector DTACK interface signal is
asserted ON (LOW). Subsequent removal of the CPU READ/WRITE command
causes the board-generated DTACK signal to return to the OFF (HIGH) state.
After board selection has occurred, three groups of VMEbus signals
control READ/WRITE communications with the board:
a. Data Bus lines D00 to D15
b. Address lines A01, A02, A03, A04
c.
Bus
Control
Signals:
1. WRITE*
2. DS0*, DS1*
3. SYS CLK
4. SYS RESET* ("*" = Asserted LOW)
Data bus lines are bidirectional and move data to or from the board
through a 16-bit data transceiver in response to control signals from the control
decoder. The data transceiver serves as a buffer for the internal data bus which
interconnects all data devices on the board.
Address lines A01 through A04 map the 16 communication registers
onto a 32-byte boundary within the VME address space (Section 4). The control
signals determine whether data is to be moved to the board (WRITE) or from the
board (READ). The control signals also provide the necessary data strobes (DS0,
DS1), and supply a 16 MHz clock (SYS CLK) for use by on-board timers. A SYS
RESET input resets all timers and flags.
Static controls are latched into the Control Register, and are used
primarily to establish the operational mode of the boards. Status flags, necessary
for monitoring and controlling the analog input multiplexer and the ADC, are read
through the Status Register. The Control and Status Registers (CSRs) are referred
to collectively as the Control and Status Register (CSR). Most of the Control
Register outputs can be monitored directly through the Status Register.
Each of the two analog output channels are controlled by writing 12-bit
right-justified data into a dedicated 16-bit READ/WRITE register. The lower 12 bits
(D00 to D11) of each Analog Output Register are loaded directly into the DAC for
the output, while the upper four bits (D12 to D15) are ignored.
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