PRODUCT OVERVIEW
Copyright 2001
2-4
DAC128V HARDWARE REFERENCE
signals. The block labeled “IPDbus DAC I/O GATEs” consists of a pair of bi-directional
bus transceivers for buffering the writes and quickly terminating read operations.
This second level “top” block diagram provides more detail to better understand the inner
functional elements of each of the quad DAC units, including the digital registration and
read-back capabilities, the buffered high and low voltage references, and the buffered
outputs to the I/O connector. Also provided in more detail (at the top of Figure 2-3) is the
ability to run this board using external (clean) power supplies, and the quad-reference
voltage generator, with individual buffers for the reference outputs to the I/O connector.
The table on the (upper half) left side of Figure 2-3 provides all of the eight valid voltage
ranges that can be selected per quad DAC unit, and their respective (centered) power-up
default voltage outputs.
2.5 Detailed Description
The DAC128V was developed using VHDL and Synthesis, targeted to an Altera EPLD,
schematic captured and integrated to standard integrated circuits, connectors, and discrete
components using VIEWLogic’s ViewDraw and associated packages.
2.6 Digital Components and their Functions
All IP Module Logic Bus transfers take place across J1, the IP Module Logic Connector,
located on the left side of all block diagrams. Refer to the
ANSI/VITA 4-1995
specifications for details about the signals on this connector. This IP Module does not
support DMA or Interrupts, and has no memory accesses.
Figure 2-4 DAC128V Layout
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Содержание DAC128V
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