Artesyn BajaPPC-750, Руководство пользователя

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4-4 BajaPPC-750: On-Card Memory Configuration
May 2002
4.4.1 SDRAM Configuration
Bits 0:3 of the Board Configuration Register (see Register Map 4-2) at FF98,0020
16
store the SDRAM bank configuration information. Bit 4 indicates whether or not
the parity option is installed. Bits 5–7 do not affect the SDRAM configuration.
A programmable logic device (PLD) maintains these configuration values, which
are determined by whether or not specific configuration resistors are physically
installed on the BajaPPC-750 circuit board. The following table describes the con-
figuration bit selections:
4.4.2 SDRAM Timing
One of the primary functions of the MPC106 is to allow flexible control of all
important DRAM timing parameters. The correct SDRAM timing for any reason-
able combination of board speed and SDRAM speed can be programmed. On the
BajaPPC-750, the timing values programmed into the Memory Control Configu-
7 6 5 4 3 2 1 0
pwr_up P2_cfg bus_spd parity bank_config mem_size
Register Map 4-2. BajaPPC-750 Board Configuration (Memory)
Table 4-3. Memory Configuration Bit Values
Bit Field Description
Bit Values
Bit 4 Bit 3 Bit 2 Bit 1 Bit0
mem_size 64MB per bank 0
32MB per bank 1
bank_config Bank 1 installed 0 0 0
Banks 1–2 installed 0 0 1
Banks 1–3 installed 0 1 0
Banks 1–4 installed 0 1 1
Banks 1–5 installed
a
a.
Currently, no configurations use more than four banks. Rev. 22 and higher boards do not support
more than four banks.
1 0 0
Banks 1–6 installed
a
1 0 1
Banks 1–7 installed
a
1 1 0
Banks 1–8 installed
a
1 1 1
parity Parity not installed 0
Parity installed
b
b.
Currently, no configurations have parity installed. Rev. 22 and higher boards do not support parity.
1