Artesyn BajaPPC-750, Руководство пользователя

Страница: 47 / 215

3-2 BajaPPC-750: Central Processing Unit
May 2002
3.1 Processor Reset
The BajaPPC-750 has a momentary two-position reset switch on its front panel.
Upon assertion of the SWRST* signal from this switch or the V_SYSRST* VME
reset signal, the HRESET* signal is asserted at the CPU and power-on reset cir-
cuitry, ensuring the proper initialization value for the DRTRY* signal. When
asserted, this signal prohibits data retrys, allowing operation of the fast L2 cache
and data streaming. In addition, the front panel switch can issue a non-maskable
interrupt to the interrupt controller programmable logic device (PLD). Software
resets are initiated by asserting the SRESET* signal at the CPU.
Bit 7 of the Board Configuration Register (see Register Map 3-1) at FF98,0020
16
indicates whether or not the reset was due to a power-up condition (0=power-up,
1=reset). After power-up, a write to the Clear NMI Register at FF9E,0000
16
sets this
bit, which is cleared only at power-up. (After power-up, wait for at least 500 milli-
seconds before writing to the Clear NMI Register.)
3.2 Processor Initialization
Initially, the BajaPPC-750 powers up with specific values stored in the CPU regis-
ters. The initial power-up state of the Hardware Implementation Dependent reg-
ister (HID0) and the Machine State register (MSR) are given in Table 3-2.
7 6 5 4 3 2 1 0
pwr_up P2_cfg bus_spd parity bank_config mem_size
Register Map 3-1. BajaPPC-750 Board Configuration (Reset)
Table 3-2. CPU Internal Register Initialization
Register
Default After
Initialization (Hex)
Notes
HID0 8000,802C Hardware Implementation Dependent
register. (See Section 3.2.1)
MSR 3032 Machine State register.
(See Section 3.2.2)