Artesyn BajaPPC-750, Руководство пользователя

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Processor Initialization 3-3
0002M621-15
3.2.1 Hardware Implementation Dependent Register
The Hardware Implementation Dependent Register, HID0, contains bits for
CPU-specific features. Most of these bits are cleared on initial power-up of the
BajaPPC-750. Please refer to the
PPC750 RISC Microprocessor User’s Manual for
more detailed descriptions of the individual bit fields. The following register map
summarizes HID0 for the PPC750 CPU:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
EMCP DBP EBA EBD BCLK res. ECLK PAR DOZE NAP SLEEP DPM reserved NHR
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ICE DCE ILOCK DLOCK ICFI DCFI SPD IFEM SGE DCFA BTIC res. ABE BHT res.
NOOP
TI
Register Map 3-2. PPC750 Hardware Implementation Dependent, HID0
EMCP Enable machine check pin. Initially enabled on the BajaPPC-750.
DBP Enable bus address and data parity generation (in conjunction with EBA/
EBD).
EBA/EBD Bus address and data parity checking enables.
BCLK Select bus clock for test clock pin.
ECLK Enable external test clock pin.
PAR Disable precharge of ARTRY* and shared signals.
DOZE In doze mode the PLL, time base, and snooping are active.
NAP In nap mode the PLL and time base are active.
SLEEP In sleep mode no external clock is required.
DPM Enable dynamic power management.
NHR Not hard reset (software only). 0=hard reset, 1=no hard reset.
ICE/DCE Instruction and data cache enables. The instruction cache is enabled on
initial power-up.