Artesyn BajaPPC-750, Руководство пользователя

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7-2 BajaPPC-750: Ethernet Interface
May 2002
7.1.1 Configuration
The Intel 21143 allows for complete initialization and configuration from soft-
ware. Write operations to reserved portions of the configuration registers com-
plete normally, discarding any data. Read operations to these areas also complete
normally, returning a value of zero. A hardware reset places the default values in
the configuration registers, and a software reset (CSR0, bit 0) has no effect. The
configuration registers accept byte-, word-, and longword-wide accesses.
7.1.2 Command/Status
The Intel 21143 command/status registers (CSRs) are mapped in host I/O or
memory space. The CSRs provide the host with pointers, commands, and status
reports. These 32-bit registers are
quadword aligned and require longword instruc-
tions. Also, the reserved bits should be written with zero to preserve compatibility
with future releases. Reading the reserved bits will produce unpredictable results.
Table 7-1. 21143 Configuration Register Summary
Hex Offset Mnemonic Function Hex Default
00 CFID Identification Register 00191011
04 CFCS Command and Status Register 02800000
08 CFRV Revision Register 02000041
0C CFLT Latency Timer Register 0
10 CBIO Base I/O Address Register undefined
14 CBMA Base Memory Address Register undefined
18-24 reserved
28 CCIS Card Information Structure Register read from
serial ROM
2C SSID Subsystem ID Register read from
serial ROM
30 CBER Expansion ROM Base Address Register XXXX0000
38 reserved
3C CFIT Interrupt 281401XX
40 CFDD Device and Driver Area Register 8000XX00
44 CWUA0 Configuration Wake-Up-LAN Address 0 undefined
48 CWUA0 Configuration Wake-Up-LAN Address 1 undefined
4C SOP0 SecureON Password (D,C,B,A) undefined
50 SOP1 SecureON Password (F,E) undefined
54 CWUC Configuration Wake-Up Command undefined
58-D8 reserved