Artesyn ATCA-7480, Инструкция по установке и эксплуатации, Страница: 151 / 330

Maps and Registers
ATCA-7480 Installation and Use (6806800T17A)
151
5.1.16.1 Internal Interrupt Status Register
5.1.16.2 Telecom Interrupt Status Register
This register reflects the status of telecom related interrupt signals. The corresponding
Telecom interrupt sources need to be enabled. Use of this register is optional, because the
same information can be found at:
Table 5-92 and Table 5-93 . These tables also show how to
clear the corresponding interrupt status bits.
Table 5-68 Internal Interrupt Status Register
Address Offset: 0x21
Bit Description Default Access
0 IPMC signals interrupt. Host clears flag. 0 LPC: r/1wc
IPMC generates host interrupt:
0: no action
1: generate minimum 175
μ s interrupt pulse
- IPMC: w
7:1 Reserved 0 r
Table 5-69 Telecom Interrupt Status Register
Address Offset: 0x22
Bit Description Default Access
3: 0 Telecom CLK_MONITOR_FINISHED interrupt:
One or more Telecom Clock measurements have
finished. - LPC: r
7:4 Telecom CLK_MONITOR_OUT_OF_RANGE interrupt:
One or more Telecom Clocks are out of range - LPC: r